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jnosewor
Visitor
Visitor
471 Views
Registered: ‎11-15-2019

Generate PS to PL interrupts external to block design

In the past I have had challenges moving IP outside of the BD into pure verilog (versus package the verilog into and  IPI component). I believe this is large in part due to how Petalinux recognizes devices in the HDF file.

I am going to be building petalinux for a design that currently exports the PS interrupts on a Zynq Ultrascale+ as an external BD interface.My suspicion is that it be problematic for petalinux that the device generating the interrupts is not in the HDF file and can not be referenced in the device tree file (I think).

I see many example where AXI-GPIO block is modified to generate a PS interrupts based on an external signal. I expect that is for good reason, and in part due to the aforementioned issue.

I was hoping to verify whether or not my thought process is correct as to not force others to unnecessarily rework the design. We are using the uio driver.

Has anyone else been success successful with using a signal to the BD as a PS interrupt with Petalinux (2019.1)?

 

Thanks in advance!

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abhinayp
Xilinx Employee
Xilinx Employee
342 Views
Registered: ‎07-12-2018

Hi @jnosewor 

You can write the solution as discussed in the SR which could be helpful for others.

Best Regards
Abhinay PS
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