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atmosfir
Observer
Observer
713 Views
Registered: ‎08-03-2018

Getting Multiple DMAs to work addressing questions

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Hello, I am trying to make 2 DMAs connected to 2 HP ports and feed the data to simple MACs. I have a working design with 1 DMA but I want to increase bandwith. However I have several questions. this is the block design

Screenshot from 2019-07-23 15-17-53.png

 

This is the address space

 

Screenshot from 2019-07-23 15-17-09.png

I left some address space empy and if i click auto assign address it will give me critical warnings as follows :

Screenshot from 2019-07-23 15-27-20.png

Understanding that my goal is to increase bandwith, my questions :

1. How to best allocate memory for 2/more DMAs?

2. On software/control side, how do we best manage concurrent/parallel AXI DMA transactions? so far I have not been able to get 2 DMAs to work.

example designs in the software side using multiple DMAs would be highly apprecieated. I have seen the "high performance video system" example design however I am still stuck.

Thank you

Screenshot from 2019-07-23 15-17-53.png
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demarco
Xilinx Employee
Xilinx Employee
675 Views
Registered: ‎10-04-2016

Hi @atmosfir ,

I think the issue in your block diagram is that axi_dma_0 and axi_dma_1 are connecting through the SmartConnect to both S_AXI_HP0 and S_AXI_HP1. This is causing both AXI DMA IPs to have multiple paths to the PS DDR address range DDR_LOWOCM and throwing the critical warnings.

You have two options to fix this:

1. Remove the connection on AXI SmartConnect from M01_AXI to S_AXI_HP1.

2. Seperate the paths between the AXI DMA IPs and the S_AXI_HPn ports. Your block diagram would end up looking like this:

https://forums.xilinx.com/t5/AXI-Infrastructure/MCDMA-or-Multiple-DMAs-Single-HP-port-or-Multiple-HP-ports/m-p/999669/highlight/true#M3531

Regards,

Deanna

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demarco
Xilinx Employee
Xilinx Employee
676 Views
Registered: ‎10-04-2016

Hi @atmosfir ,

I think the issue in your block diagram is that axi_dma_0 and axi_dma_1 are connecting through the SmartConnect to both S_AXI_HP0 and S_AXI_HP1. This is causing both AXI DMA IPs to have multiple paths to the PS DDR address range DDR_LOWOCM and throwing the critical warnings.

You have two options to fix this:

1. Remove the connection on AXI SmartConnect from M01_AXI to S_AXI_HP1.

2. Seperate the paths between the AXI DMA IPs and the S_AXI_HPn ports. Your block diagram would end up looking like this:

https://forums.xilinx.com/t5/AXI-Infrastructure/MCDMA-or-Multiple-DMAs-Single-HP-port-or-Multiple-HP-ports/m-p/999669/highlight/true#M3531

Regards,

Deanna

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