06-20-2019 08:33 AM
I'm using a Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit.
I would like to read the current value of the Physical Counter frequency, i guess this information is available in a memory mapped register, but I do not find in the documentation where?
06-21-2019 08:52 AM
The register referene is available in UG1087.
Please let us know if you are looking for the same and elaborate more on physical counter frequency .
06-24-2019 04:48 AM
Thanks for the pointer, I already found this page... But i'm getting lost in the tons of documentation.
Sorry if my questions looks stupids, but I'm not very familliar with those low levels concepts...
I want to use the APU Secure Physical timer, CNTPNS IRQ (interrupt ID 29 according to ug1085 doc).
The code i'm porting to the A53 cores of ZCU102 basically does the following:
However I first need to set the initial value of CNTFRQ_EL0 register on all A53 cores, and this value must be set to the frequency of the APU Secure Physical timer. So, my question is: Which memory mapped register should I read to obtain the APU Secure Physical timer frequency?
The other question I have is: Can this value be changed? If yes, what is the valid range for ZCU102 board?
Thanks a lot.
06-24-2019 08:56 AM
After more investigation, I did try to read the frequency from the base_frequency_ID_register (IOU_SCNTRS) Register, which contain a value closed to 100Mhz. This seems to provide me a tick every 10nsec, which is what I'm looking for.
However, if I set base_frequency_ID_register to 10Mhz, I'm still getting a tick every 10nsec... I was expecting every 100msec...
So it seems that the reference clock frequency is set elsewhere... But where?