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namabo
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Registered: ‎07-27-2018

How set up Axi Traffic Generator or HLS Master to configure and use Axi Ethernet Lite

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Hi,

I'm actually working on Artix-7 35T Arty FPGA Evaluation Kit, I made a design with an AXI traffic generator and an AXI Ethernet Lite, my purpose is generate Ethernet Traffic, and test if some packets exit from the Ethernet Phy connecting the board to a PC.

 

First of all this is the design I made:

design.png

Then I inserted a constraint relative to the eth clock:

set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports eth_ref_clk]

I'm using AXI4 interface selected for ATG and AXI Ethernet Lite.

I set the AXI Traffic Generator as :

 

axi_traffic_gen_settings.png

 

I inserted also a constant of value 1 on the core_ext_start. For test the design I connected peer-to-peer (static IP) my PC with the board and I send simply a ping.  What I'm experimenting is just that the phy led indicating the rx/tx blinks every packet is sent, so I think the physical part is working well, but on my pc I don't see anything related to the traffic that should be generated form the board by mean of ATG ( I'm sniffing with Wireshark).

So my questions is:

1) is it possible to use AXI Traffic Generator 3.0 as standalone block in master mode without a PS?

2) in order to start generating eth packets is the configuration I made enough?

 

In other examples I saw people that inserted a .coe file.

I'm little bit confused because I don't understand  which are the characteristics of the packet generated by the ATG (I mean Ip address MAC eth), and even if I have to provide the coe I dont know where to put it as input to ATG.

 

Thank you.

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namabo
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Registered: ‎07-27-2018


As I image, the solution is to wait 2/3 seconds before starting the ATG IP because the phy takes that time to start up.

I did it inserting a custom IP that driver the axi_reset_n signal of ATG every 2 seconds, in this way when I start the board after 2/3 second the phy is up and running, and the ATG (only it) is reset every 2 seconds. I can see the packet in wireshark finally every 2 secs!

 

Best regards

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6 Replies
demarco
Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @namabo,

Have you looked at the example design for the AXI Ethernet Lite? It would be much easier for you to start from that design and modify it to suit your needs than to start from scratch. From what you have shown below, your design doesn't do any configuration of the AXI Ethernet Lite. 

 

The example design is built into Vivado. You can find a description of what it does in PG135.

https://www.xilinx.com/support/documentation/ip_documentation/axi_ethernetlite/v3_0/pg135-axi-ethernetlite.pdf

 

Regards,

 

Deanna

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namabo
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Thank you @demarco,

I saw the example project, I were using ATG because I would like to follow the visual design approach, however my main goal is to manage an ethernet interface without a PS logic, and possible with the AXI bus.

 

I saw the PG135 and basically I made an HLS AXI Master to control and set the configuration of the  Ethernet module.

Ok, also this doesn't work but since the HLS approach will be my final one, I really appreciate an advice.

I have attached the simple code I wrote for the axi-master.

 

My purpose is to send always the same packet (an ICMP packet I copied from the net, just for an example), to write the code I follow the section "Software Sequence for Transmit with Ping Buffer" PG135 pag. 28.

 

In the design I have the AXI Ethernet Lite in Full Duplex mode, with base address at 0x40E00000.

In the HLS code I put "offset=off", and then in the user interface of the custom IP, I wrote the same address of the peripheral I want to control i.e. AXI Eth Lite.

 

design.png

 

After flash the board I get:

1) the led1 is on  (ap_idle=1)

2) I switch on sw1 so as to start the Master and led1 turn off and led3 turn on (ap_dile=0, ap_ready=1)

 

I sniff packet with wireshark in promiscuous mode but there aren't any signs of the packet I statically hardcoded into the AXI Master.

 

So, sad that:

Is this approach (design +  AXI Master to completely control configuration and data exchange) the right one and the simplest one to control basic data manage on the AXI Ethernet Lite?

 

When I start the AXI Master there will be just one transaction or It will continue like an infinite loop?

 

I newbie of HLS, I don't know how and when mix this together, I used the HLS method because in this way I can rely on it for the AXI bus, without write all the infrastructure by hand in VHDL.

 

Is it possible to control and configure the Axi Ethernet block just with an AXI Master HLS peripherals?

If so which are the steps to be implemented?

Thank you a lot!

 

 

 

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demarco
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Registered: ‎10-04-2016

Hi @namabo,

Designing an HLS block to configure and send data with an AXI Ethernet Lite is going to be difficult, especially if this is the first time you are using the AXI Ethernet Lite IP. What happens if you get an error back from AXI Ethernet? How does your HLS code deal with that?

 

Looking at your code, it doesn't appear to follow the Programming Sequence in the AXI Ethernet Lite PG. If you do go down the HLS path, you need to understand this programming sequence, see how the AXI Traffic Generator in the example design creates the sequence and verify that your HLS code matches these operations.

 

I'd recommend trying this in simulation first. Once you move to hardware debug, I'd recommend inserting some ILAs into you design to look at the AXI transactions between the configuration code and the AXI Ethernet Lite IP. That gives you visibility to debug issues inside the FPGA.

 

UG994 provides the details about how to insert ILAs into a Block Diagram.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug994-vivado-ip-subsystems.pdf#page=119

 

Regards,

 

Deanna

 

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namabo
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Registered: ‎07-27-2018

Hi  @demarco,

regarding this:

 

"Looking at your code, it doesn't appear to follow the Programming Sequence in the AXI Ethernet Lite PG. If you do go down the HLS path, you need to understand this programming sequence, see how the AXI Traffic Generator in the example design creates the sequence and verify that your HLS code matches these operations."

 

In PG the steps to transmit are:

 

1 The software stores the transmit data in the dual port memory starting at address 0x0
2 The software writes the length data in the dual port memory at address 0x07F4
3 The software writes a 1 to the status bit at address 0x07FC (Bit[0] on the data bus)
4 The software monitors the status bit and waits until it is set to 0 by the AXI Ethernet Lite
    MAC core before initiating another transmit
5 If the transmit interrupt and the global interrupt are both enabled, an interrupt occurs 
   when the AXI Ethernet Lite MAC core clears the status bit
6 The transmit interrupt, if enabled, also occurs with the completion of writing the
Ethernet MAC address

 

Are these enough, or there are, let's say, further hidden settings to be done?

However for sure I'll be read better the example code provided with the IP.

 

PS. In general, reading your post I understand that it would be better to follow the VHDL/Verilog way instead the HLS one, when there are low level peripheral control to do, am I right?

Also because the ap_start signal need to be externally controlled...

 

For sure I will use the ILA as you suggested.

Thank you for your reply I will take my time to try out what you have suggested!

 

 

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namabo
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Registered: ‎07-27-2018

Hi @demarco,

 

I go ahead on the analysis and I did 2 tests:

 

FIRST TEST

I did a design in which there are:

1) ATG in System Init (AXI4-Lite)

2) Axi Ethernet Lite with MII and MDIO

3) ILA

 

I feed the ATG with two .coe files made starting from the example design of the AXI Ethernet Lite IP.

In this configuration as soon as I assert the reset The ATG produces the data as shown in the images attached,

(ATG_CH1.png, eth_lite_in.png, mii_eth_frame.png) It seems right I see the data as I inserted in the coe both out of the CH1 of ATG and in input of Eth Lite block. I also see the MII with a  complete ethernet frame packet with pad automatically added with 72byte.

The problem is that I don't see anything sniffing it, I trigger the ILA on write valid signal on AXI, then I reset the board and get the waveforms.

I noticed that the status link led of the PHY tunrs on after a while (1/2 seconds) instead the AXI packet is sent as soon as the reset is asserted.

May it possible that all things are right but the packet is sent too early to respect of the phy up process?

mii_eth_frame.png

 

SECOND TEST

The structure of the design is the same of the first test, but I put the ATG in High Traffic Mode with Ethernet,

then I connected to an external switch the ext_start signal of the block.

In this case I really don't understand the waveforms of ILA, It seems that ATG write always the same word (0xC0015AFE), without take care of any protocol logic ( in this case 802.3 for example).

I would aspect , in the case the user could choose the protocol, that the packet generated had specific characteristics related to the protocol options, instead it seems that ATG just replicate this value at specific interval.

ATG_high-level-traffic_ETH.png

 

Obviously, in this manner, the AXI Ethernet Lite block doesn't produce any data on MII port.

So, Which is the right way to use this block IP?, I understand that I could put it on an AXI bus and it could produce the right packet(in this case ethernet) without meaning in data field but with the right structure. In this configuration the user can't feed any data, where does it get the data with which builds the packet?

 

ATG_CH1.png
eth_lite_in.png
mii_eth_frame.png
ATG_high-level-traffic_ETH.png
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namabo
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Registered: ‎07-27-2018


As I image, the solution is to wait 2/3 seconds before starting the ATG IP because the phy takes that time to start up.

I did it inserting a custom IP that driver the axi_reset_n signal of ATG every 2 seconds, in this way when I start the board after 2/3 second the phy is up and running, and the ATG (only it) is reset every 2 seconds. I can see the packet in wireshark finally every 2 secs!

 

Best regards

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