How to align different data width in different memories?

[kane06]

Hi, my project need to load data to a special ram with data width of something weird like 300 bit, for now I'm using a bram controller connected to CDMA. With this 300-bit width, it's clear that I cannot just connect my ram to controller directly.

Is there any solution for this issue? I'm thinking about creating a module to concatenate a group of input data to get a 300-bit output and calculate a new address.

[calebd · Accepted solution]

Hello @kane06 

It sounds like your initial idea of a custom IP would be best for this, as it sounds like a weird data-packing issue.  You might be able to get away with the AXI Data Width Converter inside of the AXI Interconnect or AXI SmartConnect, but I am not sure that will adequately handle changing to such a unique bit-width.

[kane06]

Thank you @calebd . As implemention of AXI sounds much harder, I'll keep it to a custom module and place it between BRAM controller and BRAM.