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Registered: ‎10-03-2015

How to get AXI TFT controller work with ACP port

I was trying to integrate AXI Thin Film Transistor (TFT) controller IP into the Zynq system. I am using Zedboard platform for the same.
I integrated the TFT controller with the Zynq PS in Vivado IP integrator and the connections of AXI bus were done automatically by the tool. I had used ACP port to connect the Master interface from TFT controller (tried with HP0 port also and same issue as listed below was seen). I was able to successfully port it on the FPGA and when connected the board to a VGA monitor, I could see that the monitor is detecting the output and displaying something on the screen. Till here everything was fine.

The problem comes when I am changing the image to be displayed and updating the video memory data using the Processing System (ARM A9 core on the Zynq chip). Many of the pixels are showing the updated values, but many of them still continue to show the older data, thus leading to a hazy and incorrect image to be displayed. Debugging further, I ended up trying out many things until I played with the cache controller. I disabled the L2 cache controller and it improved the image quality significantly. This led to a conclusion that due to caching, some of the data is not getting updated in the memory and hence stale data is being displayed on screen. But I am using ACP port? Isn't it supposed to ensure coherence and supply the latest data to the TFT controller? Why disabling the L2 cache improves the image quality (it is still not perfect because some dirty data still remains in L1 cache). How can we debug further.

The debug didn't end here and after going through the details of ACP bus, I understood that the coherence requires presence of certain signal values along with the transaction. The TRM mentions that "An ACP read request is coherent when ARUSER[0] = 1 and ARCACHE[1] = 1 alongside ARVALID." Looking into the bus signals in the block diagram, I found that the ARUSER signals are not present in the TFT controller while I wasn't sure about the values being driven on the ARCACHE signals. To isolate this problem, I put a small glue logic between the TFT controller and ACP port. I forced the ARCACHE[1] and ARUSER[0] signals to always remain 1. This will enforce coherence when accessing ACP. When ported on FPGA and ran the code to display image, the image quality seen was exactly what I was expecting and it was working perfectly when changing images as well.

This was an interesting finding about the working of ACP port and the limitation of using the existing TFT controller IP with it. Xilinx needs to improve the IP by adding these signals so that the IP works well in this scenario as well. For anyone who ends up in a similar situation, please follow the fix mentioned above as a workaround. Alternately, you could enable the option of "Tieoff AxUSER signals to always enable coherence" in the Customize menu of Zynq.

For the same reason HP0 port was also not working because the data from L1/L2 was not getting updated in the memory and it was reading stale data. Using instructions to flush data cache makes the image look as expected with the HP0 port.
Hope this proves useful for anyone who is finding the same issue with TFT controller.
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I used AXI TFT controller v2.0 to use TFT LCD (800x480 24bit color) with HP port.


When AXI TFT controller used with linux driver (xilinxfb.c), framebuffer may be not aligned correctly.


According to LogiCORE IP Product Guide (PG095-axi-tft.pdf), address register(AR) uses only upper 11bit among 32bit address.


During allocation of framebuffer on DDR memory, lower 21 bit should be all zero.


But linux driver (xilinxfb.c) does not check whether lower 21 bit of framebuffer physical address is all zero or not.


If 21 bit of framebuffer physical address is not zero, TFT screen can be flicker.


Please refer to line number 294-301 of xilinxfb.c at github (JunghoYoo/xilinx-zynq-zc702-linuxapplication/tree/master/tft)




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