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Registered: ‎01-13-2020

How to have Microblaze memory instruction always up to date / Post implementation simulation

Hi,

I am performing post implementation simulation with Vivado 2018.3 and Modelsim 10.6c.

Here is my workflow:

  • Just 1 time
    • Create block design with a MicroBlaze
    • Synthesis
    • Implementation
    • Generation Bitstream
    • Export hardware(and include bitstream)
  • Again and again…
    • C Coding of the Microblaze in SDK
    • Build in Debug mode
    • In Vivado associate simulation .elf with the brand new soft.elf created by building the software
    • Run post implementation simulation with ModelSim
    • It doesn’t work: The Microblaze is only reading instructions of the old .elf (not the soft.elf)

I assume that it means that Vivado is saving the previous .mem file somewhere… However, I can see that the .mem file which is in post_routage_network.sim folder is always up to date… (./post_routage_network.sim/sim_1/impl/func/modelsim/design_1_lmb_bram_0.mem)

 

The only working solution I found is to relaunch synthesis and implementation after SDK build. However it’s very time consuming…

  • C Coding of the Microblaze in SDK
  • Build in Debug mode
  • In Vivado associate simulation .elf AND THE DESIGN .elf with the brand new soft.elf created by building the software.
  • RESTART SYNTHESIS AND IMPLEMENTATION
  • Run post implementation simulation with Modelsim
  • It works…

 

Do you have a solution to avoid resynthesize my design: What is the procedure to have the Microblaze memory instruction always up to date?

PS: I also tried to edit all others .mem files that were not up to date, but it doesn’t work:

./post_routage_network.ip_user_files/sim_scripts/design_1/xsim/design_1_lmb_bram_0.mem

./post_routage_network.ip_user_files/sim_scripts/design_1/questa/design_1_lmb_bram_0.mem

./post_routage_network.ip_user_files/sim_scripts/design_1/ies/design_1_lmb_bram_0.mem

./post_routage_network.ip_user_files/sim_scripts/design_1/vcs/design_1_lmb_bram_0.mem

./post_routage_network.ip_user_files/sim_scripts/design_1/riviera/design_1_lmb_bram_0.mem

./post_routage_network.ip_user_files/sim_scripts/design_1/activehdl/design_1_lmb_bram_0.mem

./post_routage_network.ip_user_files/sim_scripts/design_1/xcelium/design_1_lmb_bram_0.mem

./post_routage_network.ip_user_files/sim_scripts/design_1/modelsim_/design_1_lmb_bram_0.mem

 

 

Thank you,

Erwann

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