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cerilet
Explorer
Explorer
780 Views
Registered: ‎08-26-2014

How to have access to 200MB of data written by an IP on the processor in Real-Time?

Hi guys,

 

I have an HLS generated IP connected to the processor HP port using an AXI-Master connection. The IP is writing the data correctly in the DDR area but this data cannot be seen updated from the processor. Only when I relaunch the program I see that the data has ben properly written.

 

I just tried using the ACP port enabling the ACP transaction checker, but it behaves similarly.

 

I think this is because I have to activate the SCU filtering to keep the data coherence. However, I have to write around 200MB of data using this IP so I cannot use the OCM.

 

Does anyone has a clue how to configure the Zynq to be able to write 200MB of data using an external IP and have this data available and updated from the processor?

 

Ah, another important point. I have to access just some of this data at certain moments and this operation has to be as fast as possible because I am performing Real-Time operations.

 

Many thanks,

 

Cerilet

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johnmcd
Xilinx Employee
Xilinx Employee
749 Views
Registered: ‎02-01-2008

It sounds like cache is getting in the way. To verify, invalidate the cache before reading the DDR via the cpu.

 

A few options that come to mind:

1. Us the HP port and mark the 200MB DDR range as non-cached in the cpu's MMU. If using baremetal, this is done in the translation_table.S (or something like that) file within the bsp.

2. use the ACP port but make sure that you are driving the AXI cache and user signals correctly in order to enable coherency. Here's an old post: https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Is-ACP-using-the-cache-on-Zynq/m-p/388439#M10284

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