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rmelo@inti.gob.ar
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How to implement burst transactions in the PS?

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Hi. I created a new package with an AXI Full interface. The template given by IP packager implement a BRAM. I wrote and read data using Xil_In32 and Xil_Out32, but the idea with AXI Full is to take advantage of burst mode. Any idea on how to do that? I did't found examples or info about that.

 

Thanks.

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rmelo@inti.gob.ar
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We checked with ILA and burst is working.

 

To summarize, to enable burst (using the BRAM controller as example):

 

 

// Set the associated memory cacheable
Xil_SetTlbAttributes(XPAR_BRAM_0_BASEADDR, 0x15de6);
...
// Write
memcpy((void *)XPAR_BRAM_0_BASEADDR,wval,BYTES);
...
// Read
memcpy(rval,(void *)XPAR_BRAM_0_BASEADDR,BYTES);

 

 

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hbucher
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rmelo@inti.gob.ar placing an AXI system cache in front of the mm slave is one easy win-win option.

https://www.xilinx.com/products/intellectual-property/axi_systemcache.html

The cortex a9 has limited support to burst

https://developer.arm.com/docs/ddi0407/e/snoop-control-unit/amba-axi-master-port-interfaces/cortex-a9-mpcore-supported-axi-transactions

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dylan
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For an ARM CPU to generate bursts, the region of memory must be marked as normal (cacheable) memory. By default in a standalone BSP, it is set as Device memory, which is appropriate for peripheral control registers.
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rmelo@inti.gob.ar
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I think that I am misunderstanding something. The main idea about to use AXI Full vs Lite is the burst feature, right? Is not solved in some Xilinx API? I need to manually add DMA or cache solutions? Burst is not used in the Zynq AXI Full implementation? I know that if a need to move huge quantities of data I can use AXI DMA in HP ports, but if I need to read a BRAM, read one by one the values is a waste, is not possible to use burst without DMA? thanks for any possible clarification XD.

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hbucher
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rmelo@inti.gob.ar read tge doc I linked

 

"Cortex-A9 MPCore master ports generate only a subset of all possible AXI transactions."

 

The ARM itself Wil give you max 8 byte bursts. The cache component will conflate them for you, optimizing the bus.

 

This is an ARM design, nothing to do with xilinx.

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rmelo@inti.gob.ar
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8 bytes I assume that is the width of the data bus. Is the AXI cache really needed? I was reading about to use PS DMA.

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hbucher
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rmelo@inti.gob.ar Needed? No. Just the easiest. It will be transparent to you. DMA is the most effective solution but you have to program it. 

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rmelo@inti.gob.ar
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I was doing some experiments and I obtain good results :-D

 

* I crated a project with BRAM controller, using the AXI Full interface (no system cache, no DMA, nothing more that the Zynq and the BRAM controller and I pushed autoconnect).
* In the PS, I made write and read operations using Xil_Out32/In32 and memcpy. The use of memcpy reduced the access time almost 2.35 times.

* I followed this post to enable cache in the address of the BRAM controller. The access time with Xil_Out32/In32 was reduced almost 5 times... and with memcpy almost 66.5 times :-) (so, between Xil_Out32/In32 and memcpy was reduced almost 30 times).

 

I will do a better test and check with ILA, but I suppouse that the burst transaction was enabled.

 

Regards.

 

PS: when confirmed, I will mark the post as solved

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dylan
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Correct. Bursts are created by changing the MMU/translation table settings for the PL address range by marking the region as a normal memory type, usually to enable the cache.
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rmelo@inti.gob.ar
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We checked with ILA and burst is working.

 

To summarize, to enable burst (using the BRAM controller as example):

 

 

// Set the associated memory cacheable
Xil_SetTlbAttributes(XPAR_BRAM_0_BASEADDR, 0x15de6);
...
// Write
memcpy((void *)XPAR_BRAM_0_BASEADDR,wval,BYTES);
...
// Read
memcpy(rval,(void *)XPAR_BRAM_0_BASEADDR,BYTES);

 

 

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