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2U3
Explorer
Explorer
801 Views
Registered: ‎05-25-2020

How to perform simple AXI DMA

Hello,

Could anyone please tell me how to set up to perform simple AXI DMA?

I'd like to transfer a data stored in a buffer in a top module to DDR, and transfer back that from DDR to another buffer.

The buffers are [31:0] buff_o[256] and buff_i[256] in a top module.

If there is an exact same sample as this, please show me where it is.

Or,

please give me more detail explanation about "Direct Register Mode" MM2S described on p.70 in PG021 June 14, 2019.

A destination address seems not to be set while a source address is set to MM2S_SA. How one set destination address? And when the source is a buffer in a module as show above, how to set the one?

Thank you.

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@2U3 

This isn't exactly what you asked for but it does demonstrate the AXI DMA.  The data path is PSDDR-to-PL (PSDDR > AXI Data Stream FIFO) and from the PL-to-PSDDR (AXI Data Stream FIFO > PSDDR).  I hope this helps.

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2U3
Explorer
Explorer
711 Views
Registered: ‎05-25-2020

Thank you for you helpful comment.

Then, could you please answer the questions listed below?

Q1. When configure AXI DMA via AXI-Lite, which is easier run linux or baremetal on PS?

Q2. There seems to be no explanation about C_BASEADDR in pg021. Is C_BASEADDR the one that I should set somewhere, or I get from somewhere?

Q3. In case of configuring AXI DMA using a module, to set 1 to S2MM_DMACR.RS, is the sequence shown below correct?

reg [31:0] var_dmacr;

load a data from S2MM_DMACR into var_dmacr, using AXI-Lite interface.

var_dmacr <= (var_dmacr & 0xFFFFFFFE) + 1;

store a data in var_dmacr into S2MM_DMACR, using AXI-Lite interface.

Thank you.

 

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2U3
Explorer
Explorer
694 Views
Registered: ‎05-25-2020

Hello,

I tried making a design shown below, and the design has been validated. But Master Base Addresses are all 0x0000.

Could anyone please tell me the correct ones?

Thank you. 

diagram_axidma_2.png
addr_edit.png
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miker
Xilinx Employee
Xilinx Employee
649 Views
Registered: ‎11-30-2007

@2U3 

I used baremetal.  I created the example HelloWorld design and then used the xsct to read/write from the Cortex-A9 APU.  By running the HelloWorld design, you initialize the PS FCLK clocks which the PL expects.

I have attached a Vivado 2020.2 Project Archive that I utilized.  You can see that in my case, the AXI DMA C_BASEADDR is mapped to 0x4040_0000.

If you follow the commands I had in the referenced Forums Post, those will provide all the steps necessary which includes the Run/Stop control.

 

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Embarrased
Newbie
Newbie
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Registered: ‎03-09-2021

  • Open the base project in Vivado.
  • In the Flow Navigator, click “Open Block Design”.
  • The block diagram should open and you should only have the Zynq PS in the design.
  • Click the “Add IP” icon and double click “AXI Direct Memory Access” from the catalog.
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2U3
Explorer
Explorer
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Registered: ‎05-25-2020

Thank you, but your tutorial and sample seem to be for the way how to control AXI DMA from PS, while I'd like to do that from PL.

Thank you.

 

 

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2U3
Explorer
Explorer
504 Views
Registered: ‎05-25-2020

Thank you, but my issue is whether all the Master Base Address being 0000 is OK or not.

Thank you.

 

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Rmccarty
Adventurer
Adventurer
478 Views
Registered: ‎09-05-2020

No, the addresses should not be zero. You are missing the connection between the ps axi master and the axilite interface on the dma. Add another axi interconnect to the block diagram and connect its input to the ps axi master out and then the output to the dma axilite input.