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Registered: ‎08-02-2019

How to run AXI Master example design as Cyclic mode instead of single shot?

Hi everybody,

In summary:

I'm using AXI-Lite Master interfaces for sending data from PL side to PS side with AXI-Lite Master Example Design, I can transfer data one shot successfully, but I need to continous data transfer mechanism.

How to run AXI Master example design(Lite or Full does not matter) as Cyclic mode instead of single shot?


IN Detail:

I need to continously transfer data from PL to PS side. In PL need to make some calculations and turn results to again PL from PS 

PL ---> PS

PL<--- PS

I have only 4 values to transfer(servo motor positions). That's why I think instead of DMA transfer through DRAM, shared OCM memory is enough and easier way for me.

At the moment I can send data from PL to PS side(AXI-Lite Master), in PS(Bare Metal) I making some calculations and send back this results to PL by using AXI-Lite Slave Interface.

All works fine but I can send data from PL to PS(AXI-Lite Master) only one time. For example, my register values are like this:

First time: 0, 1, 2, 3

But I need a cyclic control mechanism and need to renew everytime this values as Second time: 4, 5, 6, 7

Third time: 8, 9, 10, 11

I looked into AXI-Lite Master Example Design and realized, it is written to run only one time.

There is a variable start_single_write in example design, It runs mechanism only one time.

I think about a solution:

- Normally INIT_AXI_TXN input parameter starts our core, I'm planing to call this parameter recursively. 

First I set INIT_AXI_TXN = 1, then 0, then waiting for TXN_DONE = 1 output(it means transfer completed successfully), then again set INIT_AXI_TXN = 1, so dass start second call.

- instead of local counter, I ll use a global number generator register. 

If this way works, I do not need to manage neither VALID nor READY signals and I prefer this way.

In example design there is a paragraph and I'm confused to continous transfer:

// Since only one outstanding transaction is issued by the user design,
// there will not be a collision between a new request and an accepted
// request on the same clock cycle.

What do you think, Does this way work properly or do you have a better advice to me?


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2 Replies
Registered: ‎05-21-2015


This sounds more like something that would be appropriate for an AXI-lite slave, rather than the AXI-lite master.

When you send the data to the PS side, does the CPU use it immediately?  And if not, why not let the CPU read it when its read to?  (i.e. AXI-lite slave)  It's sort of the whole purpose for having such a slave in the first place.


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Registered: ‎08-02-2019

Hi @dgisselq ,

Thank you for your quick reply.

I drawed my data flow, and described it step by step. You can find it as attachment.



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