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Participant
Participant
4,539 Views
Registered: ‎05-07-2009

How to simulate a design with ppc sub-module in modelsim?

Hello, everyone,

 

My ppc440 design in XPS and other sub-modules in ISE have simulated and verified in modelsim in my previous work separately. Now I want to simulate in behavioral model the project in ISE which are the combination of these two parts. By the way, I add my ppc440 design to ISE project using "Add Sourc..." to add my XPS project file system.xmp.

 

I try to simulate this project in the way that is generating behavioral simulating model and calling the modelsim simulator in ISE. But there some errors in modelsim says that my ppc440 module dose not exist when modelsim execute "vsim -t 1ps   -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work dencrypt_ppc_top_tb glbl"

 

I hope somebody  would tell me the right flow to simulate this kind of project.

 

Thank you very much!

 

Best regards,

Aaron.

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4 Replies
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Explorer
Explorer
4,519 Views
Registered: ‎08-29-2008

Re: How to simulate a design with ppc sub-module in modelsim?

Hi aaron_eda,

 

Do you instantiate the XPS-Subsystem in your ISE-Toplevel design file as following:

 

--- Snip system.mhs ---

PORT sys_clk=sys_clk, DIR=I, SIGIS=CLK

PORT sys_rst=sys_rst, DIR=I, SIGIS=RST

...

--- Snip system.mhs ---

 

--- Snip xyz_top.vhdl ---

component system

  port(

    sys_clk : in std_logic;

    sys_rst : in std_logic;

    ...

  );

end component;

 

ppc_subsystem_inst : system

  port map(

    sys_clk => sys_clk,

    sys_rst => sys_rst,

    ...

  );

--- Snip xyz_top.vhdl ---

Rgds,

Kai

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Participant
Participant
4,510 Views
Registered: ‎05-07-2009

Re: How to simulate a design with ppc sub-module in modelsim?

Hello, Kai.

 

Yes, I instantiate my XPS sub-system in my top-module in the same way, but I use verilog HDL rather than VHDL. 

 

Do you know how to simulate this kind of ISE project using modelsim?

 

Best regards,

 

Aaron.

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Explorer
Explorer
4,398 Views
Registered: ‎08-29-2008

Re: How to simulate a design with ppc sub-module in modelsim?

Hi,

 

Excuse me for the late message, I had vacation!

Is the problem still up to date???

 

Which module (toplevel or XPS-Subsystem) did you write in verilog ??

 

Rgds,

Kai

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Participant
Participant
4,359 Views
Registered: ‎05-07-2009

Re: How to simulate a design with ppc sub-module in modelsim?

Hi, Kai

 

Thank you very much. I have solved those problems in my simulation.

 

Aaron. 

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