I have very little experience in FPGA (and in digital design!).
As part of a research project I have to add to an existing microblaze system, implemented on spartan 3 starter kit board, a pulse programmer (PP). A PP is a system that outputs a given pattern to a set of digital lines for a given time and then changes the pattern according to a program.
There are several ways of implementing the PP but I have decided to use what seams to me to be the simpler on: two blocks of RAM, say 2K deep and 16 bits wide, pointed by the same address counter. One block holds the time duration and the other the bit pattern. The control block load's the contents of the first ram into a counter and latches the content of the second one to the output. When the counter reaches the end, the AC in incremented and the next time and pattern words are loaded.
The IP access to RAM must be fast (this determines the time resolution of the PP), but the access of the processor can be slow, since this is done only once at the beginning of the experiment to write the programming words and then the IP works by is one.
I was thinking on using BRAM to hold the data. Is this a good choice? My other question is, what is the easiest way to implement microblaze access the ram? I appreciate any commets on this.
I also appreciate if you could point me to somme examples or application notes of a similar system (not a PP, but a system were memory is accessed by an IP and microblaze), were I can get somme ideas.