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maurimum
Observer
Observer
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Registered: ‎11-16-2012

Image filter with TRD 2014.4

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Hello,

 

I'm working with an image embedded system with the Zc702 kit, I'd like to implement my own image filter IP following the steps in TRD 2014.4 design(http://www.wiki.xilinx.com/Zynq+Base+TRD+2014.4) is it possible to just replace the image_filter by default (sobel detector) by my own IP in the Vivado tool?

 

image_filter.jpg

 

 

 

I mean use all the files that were pre builded and then I can just modify the hardware part with Vivado HLS and Vivado and generate the bitstream file and put it together in a package. This is the first level of my research just to verify the functionality of my image processing and then pass to the next level and work on PS part of the system(GUI, Control processor,etc)

 

greetings...

maurimum

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ckohn
Xilinx Employee
Xilinx Employee
16,708 Views
Registered: ‎12-08-2011

Yes, you can do that. Just implement your own algorithm in Vivado HLS, export the image filter IP core and replace it with the one under hardware/vivado\srcs\ip\xilinx_com_hls_image_filter_1_0. Then rebuild the Vivado project by running the project.tcl script.

 

Note that Vivado HLS will create a zip file for the exported IP core. You need to remove the old IP core in the above mentioned location and then unzip the new core there. Also, make sure you use the same IP core name when exporting the core, otherwise the Vivado IPI script will error out.

 

You could also manually remove the old core from the IPI block diagram, then import the new IP core in Vivado and add it to the block diagram but then you need to rewire the core interfaces and signals and save the new block diagram to a tcl script.

 

Depending on the complexity of your IP core, some more work needs to be done on the driver and/or application side to make things work.

 

You can also look here for other HLS generated IP core examples:

http://www.wiki.xilinx.com/XAPP1231+-+Partial+Reconfiguration+of+a+Hardware+Accelerator+with+Vivado+Design+Suite

 

Chris

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ckohn
Xilinx Employee
Xilinx Employee
16,709 Views
Registered: ‎12-08-2011

Yes, you can do that. Just implement your own algorithm in Vivado HLS, export the image filter IP core and replace it with the one under hardware/vivado\srcs\ip\xilinx_com_hls_image_filter_1_0. Then rebuild the Vivado project by running the project.tcl script.

 

Note that Vivado HLS will create a zip file for the exported IP core. You need to remove the old IP core in the above mentioned location and then unzip the new core there. Also, make sure you use the same IP core name when exporting the core, otherwise the Vivado IPI script will error out.

 

You could also manually remove the old core from the IPI block diagram, then import the new IP core in Vivado and add it to the block diagram but then you need to rewire the core interfaces and signals and save the new block diagram to a tcl script.

 

Depending on the complexity of your IP core, some more work needs to be done on the driver and/or application side to make things work.

 

You can also look here for other HLS generated IP core examples:

http://www.wiki.xilinx.com/XAPP1231+-+Partial+Reconfiguration+of+a+Hardware+Accelerator+with+Vivado+Design+Suite

 

Chris

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maurimum
Observer
Observer
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Registered: ‎11-16-2012
OK, thanks I'll try it and let you know about the results. But, I have a more question, do I need to use the Petalinux tools to create the bootable image for linux exclusively? or I can use just SDK tools to do it?( by just modifying the bitstream file with the changes in Vivado and Image_filter). Currently I'm working on Windows OS

Greetings
maurimum
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ckohn
Xilinx Employee
Xilinx Employee
9,012 Views
Registered: ‎12-08-2011

You can use XSDK to generate BOOT.bin which consists of FSBL, bitstream, and U-boot. You simply point to your own bitstream and use the pre-built FSBL and U-boot executables that are shipped with the TRD.

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