01-25-2021 01:50 AM
I am using Zynq UltraScale+ ZCU102 evaluation board for my project. I want to add an interrupt to the processor sub-system. the signal in question comes from a custom IP block written in Verilog.
I ve made all the neccesary connections and the device-tree has the following modifications
clock-names = "s00_axi_aclk","device_clk"; clocks = <0x3 0x4b 0x4b 0x0>; compatible = "generic_uio"; interrupt-parent = <0x4>; reg = <0x80010000 0x1000>; interrupts = <0 110 4>; xlnx,s00-axi-addr-width = <0x4>; xlnx,s00-axi-data-width = <0x20>;
However, the interrupt corresponding to the above block is not getting registered in /proc/interrupts.
Where am I going wrong?
01-25-2021 02:03 AM
Having a simulation model of your design might show where and why the error is occurring.
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
02-04-2021 08:35 AM
I would recommend to test with a baremetal application. You will not find information as there is no support for custom IP interrupts or interrupts external to MPSoC. I see the interrupt ID as 110 in the devicetree, the interrupt IDs for the PL_PS_GROUP0_IRQ is 121:128 and PL_PS_GROUP1_IRQ is 136:143, so GIC - 32 is the interrupt IDs (i.e. PL_PS_Group0 121-32 = 89) .
Do you have more interrupts connected to GIC in your design?