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Explorer
Explorer
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Registered: ‎11-16-2012

Issue with FIFO Generator in vivado 15.3 !!

Dear Colleague,

 

I hope I can get your attention for this issue !! 

 

In FIFO-Generator I see some unexplained behaviour!!

 

in Simulation:

Write data count (with more accurate data count option selected) I see that it does not update with the write clock cycle,(so if fifo debth is 16384 then it shows maximum data count of 8192), Which I think is incorrect(as per pg057-fifo-generator.pdf page number-17) and also when I do the real test on the firmware it shows the correct number.

similar is the case with Read_count, (in real firmware it shows the default(starting) value of 2 while as per same document it should be zero!!)

 

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Also I have been struggling to find the reason for unusual beviour of my bitfile in my last posthere!

https://forums.xilinx.com/t5/General-Technical-Discussion/Generating-correct-bit-file/td-p/662757 

 

What I found is issue with empty signal in fifo, I dont know but what is wrong here but one thing is pretty clear with my repeated test that when I donwload the bit file for the first time, my empty-signal from the fifo does not rise just before last data is read out(it rise much before this!).But multiple download somehow fix the issue and I get everything fully sychronous as per needed by my design!!.

 

I hope to get some comment from you on this issue!!

 

With Regards

 

 

 

 

 

 

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