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Registered: ‎04-15-2019

LPD DMA and cached DDR

Hi all,

 

I'm working on a bare metal application on the Ultrascale MPSoC and have a basic question regaarding cached DDR memory and DMA.  I'm going to need to DMA DDR memory from a cached region (data written by the APU) to a non-cached destination.  Is it possible for the LPD DMA to correctly read the DDR memory without a manual flush before kicking off the DMA transfer?  Google searches seem ot indicate that it can't be done.

 

Thanks,

John

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