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sam025023
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Registered: ‎11-11-2013

LVDS output issue on zynq

Hi All,

 

I try to get LVDS different output pairs from zynq device. And  Utility Differential Signaling Buffer IP is used in my design (vivado2014.1). The IO std of these different output are set to LVDS_25. The picture of vivado design is attached.  

 

By measuring the signal waveform by a oscilloscope, the signal directly from the single ended ouput is correct(like the signal o_adc_cnv). But the differential outputs (like O_DS_CNV_CH1_P) from the Buffer IP is wrong.

Any idea?

Thanks in advance.

 

Sam

 

 

LVDS_Issue.PNG

 

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mcgett
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Registered: ‎01-03-2008

What do you mean by "differential outputs ... from the Buffer IP is not right"?  What is exactly is the problem?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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sam025023
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Thx for your reply. 

I revised my words:

By measuring the signal waveform by a oscilloscope, the signal directly from the single ended ouput is correct(like the signal o_adc_cnv). But the LVDS differential outputs (like O_DS_CNV_CH1_P) from the Buffer IP is wrong.

 

For instance, an pulse is expected at single-ended pin "o_adc_cnv". But the LVDS ouput pins O_DS_CNV_CH1_P and O_DS_CNV_CH1_N don't show the correct waveform. The signal at LVDS pins always show low level voltage(~0V) without connecting anything. 

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austin
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Have you checked your errors and warning messagezs in the reports?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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sam025023
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The vivado project has no error. The synthsis and implementation are both successfully. Should I pay attention to any particular warnings? 

thx.

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austin
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Yes,

 

Every warning must be looked at, and accepred as not a problem, at least once.


For example, leaving something unconnected will cause anything to that node (pin) to be removed, and everything driving it to be removed.  You get a warning.  The design may be entirely empty.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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sam025023
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I have to say my design is not that good. it contains too many warnings. I checked them, but didn't find obvious warning related.

 

Now with the same source signal from Zyqn, one is connected to a single-ended pin, and other to LVDS output pins.

 A single-ended pin output is correct. It means the source signal is working properly. But the LVDS output pins don't work correctly. Something wrong with IO setting or Buffer IP?

 

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austin
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Most likely,

 

The IO standard is not correct, so the OBUF may be removed.  Look for that warning.

 

If the LVCMOS is correct, go back to the constraints guide, or the RTL (verilog or VHDL) and check if the correct syntax is there.

 

Do you specify the IO standard in the top RTLL module, or do you specify it in the constraints (xdc) file?

 

If you do not specify it at all, it defaults to LVCMOS (but you get a warning when it does that).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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sam025023
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The IO standard is set up by I/O ports window. The differential output pins are set to LVDS25.

 

Hereby the picture FYI.

 

 

IOStandard.PNG

 

In the constraint file, I found these corresponding constraints:

 

set_property IOSTANDARD LVDS_25 [get_ports {IDS_CH1_SDI_N[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {IDS_CH1_SDI_P[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {O_DS_CNV_CH1_P[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {O_DS_CNV_CH1_N[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {ODS_CLK_CH1_P[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {ODS_CLK_CH1_N[0]}]

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austin
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s,

 

Whie in the design, go to the tcl command line and enter the get_prots that is in the script by hand for one port.  Check to see if it returns the right information (check that these are executing properly).

 

TCL is your friend here, as you may get_ports, get_pins and get_properties to verify everything is working.

 

As the default is LVCMOS, that may work just because yu never set anyhing properly.

 

To get nothing at all out means that it is being removed most likely.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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gszakacs
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Also since you're seeing the problem in hardware, make sure that Vcco for the bank containing these ports is 2.5V as indicated in the Vcco column.

-- Gabor
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sam025023
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Hi Austin

 

I tried to use the tcl command of get_property IOSTANDARD for the ports.

 

The resluts shows they are in LVDS_25 standard. They seem corret.

get_property.PNG

 

 

 

Hi Gabor,

to your advice "Also since you're seeing the problem in hardware, make sure that Vcco for the bank containing these ports is 2.5V as indicated in the Vcco column."

 

All the differential ouput ports show Vcco is 2.5, however the input port "IDS_CH1_SDI_P[0]" and "IDS_CH1_SDI_N[0]" don't show any value for Vcco in I/O ports window. Could it be an issue?

 

thx

Sam

 
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austin
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OK,

 

Well, no, it doesn't matter about the input port Vcco (not a concern).

 

So outputs are configured proerly, and powered.

 

0v is is then impossible.  It must be  +/- 200mV from the Vcm, which is ~200 mV.

 

So now, that gets back to how you measure?  If single ended works, then LVDS must work.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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sam025023
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Hi Austin

Thx again for your reply.

 

Without connention any load, the LVDS ouput pins are measure by an oscillascope.

Oscillascope setting: DC coupling, impedance is set to 1Mohm...

 

Width the same input source, both single-ened output and LVDS_25 ouput pins are measured, and the resluts are shown in the pict attached.

 

The single-ended output pins show pulses correctly. But LVDS outputs don't work properly. The red curve in the middle is the voltage difference betwen LVDS P port and N port. It seems there is voltage difference between P and N pins. 

 

 

 Update:

I added 100 Ohm termination cross the LVDS P and N output pins. But still get ~0V at LVDS P and N output pins..

Odd?

 

 

 

voltageMeasure.JPG

 

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gszakacs
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"All the differential ouput ports show Vcco is 2.5, however the input port "IDS_CH1_SDI_P[0]" and "IDS_CH1_SDI_N[0]" don't show any value for Vcco in I/O ports window. Could it be an issue?"

 

What I meant was to measure the Vcco actually supplied to the bank containing the LVDS_25 outputs on your board, and make sure that it is actually +2.5V.  If this voltage is not correct, then the LVDS_25 outputs will not operate correctly.

-- Gabor
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sam025023
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How can measure the Vcco for LVDS power supply? Sorry for this dummy question..

 

Some updates:

I'm using zedboard for the design. And the LVDS pins tested in my design are in Bank-13. The schematic of the zedboard shows all the Vcco_13 pins are connected to VCC3V3. 

Does it mean all the pins in bank13 can NOT be configured to LVDS_25 standard? 

thx.

 

 

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muzaffer
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>> Does it mean all the pins in bank13 can NOT be configured to LVDS_25 standard?


There is no LVDS_25 standard. LVDS is the same regardless of what the voltage level of the IO bank which is driving it. The importance of setting the LVDS_33 or LVDS_25 is to let the FPGA know how to correctly drive the necessary and unique LVDS levels correctly. If you lie to the FPGA by telling it that the IO voltage is 2.5V and supply 3.3V to the IO, the results will not make you happy. Change your LVDS_25 setting to LVDS_33 (or what ever IO type string is necessary for 3.3V IO voltage).
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sam025023
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The only IO standard option available @3.3V  is TMDS33. I tested the pins with TMDS33 standard. It still doesn't work. Vocm=~0V at both P and N pins with 100ohm terminator connected in between.

 

 

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beandigital
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As far as I am aware Zynq only has LVDS_25, so you need 2.5V. If the bank has 3.3V then thats not going to work. If you where using input then you could use 3.3V as long as the termwas external. See page 11 of datasheet.

 

Jon

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sam025023
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Thanks for your reply. 

The goal is to have different ouput pins (not limited to LVDS_25) from this bank-13.

Now the bank -13 has 3.3V.  So I chose the differential IO standard TMDS33(the only option for 3.3V differential ouput).  But it doesn't work out. 

Any ideas? thx

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beandigital
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You have to use the correct IO standard for what you are interfacing. What are you interfacing? Do you need a differential standard? TMDS33 isnt really a general standard. Why dont you just try to use LVCMOS33 to start with and see if you can see a pin toggling? If you cant then the issue is more than likely your design as long as the board is functional.

 

Jon

sam025023
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Jon, 

To your questions:

You have to use the correct IO standard for what you are interfacing. What are you interfacing? Do you need a differential standard? TMDS33 isnt really a general standard. 

To interface a peripheral with different ios. The peripheral is not finally determined. So we want to test the differential IOs from zynq first. 

 

Why dont you just try to use LVCMOS33 to start with and see if you can see a pin toggling?

 

yes, I tried LVCMOS33 output for the pins. It works.

 

 

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beandigital
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Well you cant use the LVDS in that bank (at least not the outputs) as the voltage is wrong. You may as well forget using TMDS unless you plan to use hardware that requires that standard. 

 

Jon

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austin
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s,

 

Even if the Vcco is the wrong value, if programmed for LVDS, the pins will wiggle (not be identically 0 volts).  The logic doesn't know what the voltage is, so the circuits will function, even if they do not meet the specifications.

 

All I can imagine is that your constraints or RTL are resulting in an error, and the IO is left unconfigured (and is removed).


Again, look for such a warning, error in the placement reports, DRC checks, etc.

 

As it is so stubborn, it is probably right in front of you, and you are not noticing it.

 

Looks at EVERY .rpt file.

Austin Lesea
Principal Engineer
Xilinx San Jose
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beandigital
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But how is he going to use LVDS if its out of spec? You seem to be saying that its ok to use whatever voltage you want. If he is just playing around that may be ok, but for a real design he couldnt do that.

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gszakacs
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He might want to check out this thread:

 

http://forums.xilinx.com/t5/7-Series-FPGAs/Differential-Output-Clock-from-a-3-3V-HR-Bank/m-p/471946/highlight/true#M5092

 

It looks like TMDS_33 could work, but would need special termination.  It's not clear why an LVDS output would stay at or near ground unless he's using a tristate output buffer and it's pulled down by the scope probes.  Otherwise I'd expect levels closer to the 1.6V to 1.8V range because of the Vcco being higher than required for the output standard.

-- Gabor
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austin
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b,

 

He is getting 0 volts.  I am not saying to use the wrong vcco voltage.  I am saying that to troubleshoot the problem, even with the wrong voltage (3.3 instead oof 2.5) he will still get a pin that wiggles (not 0 volts).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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llchr
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@austin wrote:

b,

 

He is getting 0 volts.  I am not saying to use the wrong vcco voltage.  I am saying that to troubleshoot the problem, even with the wrong voltage (3.3 instead oof 2.5) he will still get a pin that wiggles (not 0 volts).

 

 


wrong, I've just been "bitten" by this thinking that I could live with the slightly wrong levels in exchange for more 3.3V IOs 

 

Simple LVDS_25 output  on a microzed, verified that it works with Vcco at 2.5V

 

Vary the Vcco, if it is above ~2.9V the output shuts off and goes to zero !

 

I'd love to know the FPGA knows the voltage and if there is a magic setting that will override it

 

 

 

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austin
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That is a mystery...

 

Changing a 2.5v Vcco to 3.3v and the programnmed and working LVDS stops?

 

I have no idea how the device woukld be able to "know" the difference, and react to it.

 

If it is doing that, it was not intentional!

 

It is only gauranteed to work at the voltages specified, so what it does at unspecified voltages is, well, unspecified.  But based on what I have seen in my years as an IC designer, changing the Vcco on an LVDS output affecetd specification, but not function in previous families.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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gszakacs
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The only thing I can think of is that the LVDS output driver uses at least one other voltage, perhaps Vccaux, and increasing the Vcco causes some part of the structure to turn off.  On the other hand, 2.5V is already higher than Vccaux, so how this would happen when you increase Vcco is not clear.

-- Gabor
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