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kosinventas
Visitor
Visitor
289 Views
Registered: ‎01-21-2020

Last data word from AXI-Stream Master not received by slave AXI DMA 7.1 LogiCORE IP

Hello,

I am trying to debug a design which implements the AXI DMA v7.1 LogiCORE IP. The DMA IP is configured as shown in the attached screenshot.

The intention is for the AXI Stream master to transfer a total of 68 bytes, divided into 17 32-bit words to the AXI Slave (in this case, the DMA). But the final data word is not received, the DMA only reports receiving 64 bytes. The missing data word corresponds to the data word when tlast is asserted (i.e. it's always the final word of the data transfer), and the error occurs every time data is transferred. We have reviewed the code of the design, which interfaces with the DMA and have not discovered any glaring mistakes. Can this be e.g. a DMA configuration error?

Any advice would be greatly appreciated.

Thanks!

dma_config.png
fullstream.png
axistream.png
sendstream.jpg
tlast.png
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1 Reply
joancab
Advisor
Advisor
273 Views
Registered: ‎05-11-2015

 

You may need to select 'unaligned transfers' and/ or reduce the burst size to 2 or even 1. Alternatively you could send extra dummy words. The problem is that 17 is such an unfortunate number in binary.