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Newbie
308 Views
Registered: ‎02-24-2020

Line 41: Signal regs[0][31] in unit REGFILE is connected to following multiple drivers

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Hello here is my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------

entity REGFILE is

port
(
out1 : out std_logic_vector(31 downto 0);  
out2 : out std_logic_vector(31 downto 0);
regselect1 : std_logic_vector(4 downto 0);               --select for out1 
regselect2 : std_logic_vector(4 downto 0);               --select for out2
input : in std_logic_vector(31 downto 0);  
WE : in STD_LOGIC;                                       --write enable
regselectw : in std_logic_vector(4 downto 0);            --reg. select for writing
reset : in std_logic;
clk : in std_logic 
);

end REGFILE;

----------------------------------------------------------------------------
----------------------------------------------------------------------------


architecture reg_arch of REGFILE is

--t3ref ll registers
type regs_storage is array ( 0 to 31 ) of std_logic_vector(31 downto 0);
signal regs: regs_storage := (others => X"00000000");
---------------------------------------------------------------------

begin
 
 
 --reset process-------------------------------------
 process (reset) is
 begin
 
 if reset='1' then
 regs(to_integer(unsigned(regselectw))) <= input;
 end if;
 
 
 end process;
 -----------------------------------------------------
 
 --input process--------------------------------------
 process (clk) is
 begin
 
 if rising_edge(clk) and WE='1' then
 regs(to_integer(unsigned(regselectw))) <= input;
 end if;
 
 
 end process;
-------------------------------------------------------

--output process--------------------------------------
 process (clk) is
 begin
 
 if rising_edge(clk) then
 
 out1 <= regs(to_integer(unsigned(regselect1)));
 out2 <= regs(to_integer(unsigned(regselect2))); 
 
 end if;
 
 
 end process;
-------------------------------------------------------


end reg_arch;

however I face the error Line 41: Signal regs[0][31] in unit REGFILE is connected to following multiple drivers

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1 Solution

Accepted Solutions
Highlighted
298 Views
Registered: ‎06-21-2017

You need to combine the reset process with the input process.  Try something like:

 
 --input process--------------------------------------
 process (clk) is
 begin
 if rising_edge(clk) then
if reset='1' then
regs(to_integer(unsigned(regselectw))) <= input;
elsif WE='1' then regs(to_integer(unsigned(regselectw))) <= input; end if;
end if;
end process;

View solution in original post

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1 Reply
Highlighted
299 Views
Registered: ‎06-21-2017

You need to combine the reset process with the input process.  Try something like:

 
 --input process--------------------------------------
 process (clk) is
 begin
 if rising_edge(clk) then
if reset='1' then
regs(to_integer(unsigned(regselectw))) <= input;
elsif WE='1' then regs(to_integer(unsigned(regselectw))) <= input; end if;
end if;
end process;

View solution in original post

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