MIO and XADC pins in ZYNQ 7Z030

[peterjohn]

I am working with PCB layout for XC7Z030FFG676 package.

I know that PS_MIO[0:15] located in MIO Bank 500 and PS_MIO[16:53] located in MIO Bank 501 but how about pin map of MIO pins to UART, Ethernet, and SPI. In which document I can find the pin mapping ?

I am also looking for pin assignment of XADC differential channels VAUXP/N [0:15] to the XC7Z030FFG676 package. 

[katsuki · Accepted solution]

Hi @peterjohn 

UART, Ethernet, and SPI pins are Multiplexed and can be assigned to any MiO.

Regarding the allocation of MIO, it is good to see "2.5.4 MIO-at-a-Glance Table" of UG585 "Zynq-7000 SoC Technical Reference Manual".

Before fixing the pin assignments on the board,

 it is also recommended to use Vivado to verify MiO assignment is possible and refer to the schematic of the evaluation board.

Please refer UG865 "Zynq-7000 SoC Packaging and Pinout Product Specification" for the XADC pins.

ASCII files are available here.

Thank you

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