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beuny@vvdn
Visitor
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Registered: ‎08-06-2018

MIO to GPIO Mapping for Xilinx MPSoC

Hi

We are using XCZU4CG-SFVC784-1-e  Xilinx Zynq Ultrascale+ MPSoC. It has got 78 MIOs and 96 EMIOs.

Can anyone help to undersatnd how these MIOs /EMIOs can be mapped to GPIOs..?

For ZCU102 Board, the Calculation Formulae is baseN + EMIO next (96) + MIO(78).

96 EMIO [3 banks [b0,b1,b2] of 32 pins = 3*32] + 78 MIO [3 banks [b0,b1,b2] of 26 = 3*26].BaseN is equal to 338.

Can we use the same for any MPSoC....?

Please help......

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stephenm
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Registered: ‎09-12-2007

I have discussed the pin mapping in the forum post below.

https://forums.xilinx.com/t5/Embedded-Linux/GPIO-control-in-Linux-sysfs/td-p/833075

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