cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
5,232 Views
Registered: ‎08-04-2016

MPMC in EDK 14.7

Hello All,

 

I am using MPMC in EDK for one of my project.I have created Microblaze system with PLB based.

Taken one MPMC IP core from EDK IP catalog and connected this to PLB bus of Microblaze.

Netlist is properly generated in EDK but when I implement design in ISE I get following error

 

ERROR:Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
BIDIR, DRIVE_STR = 12
rzq


ERROR:Place:382 - The placer was unable to find a feasible solution for the IOBs
in your design. This is possibly due to SelectIO banking constraints.


ERROR:Place:418 - Failed to execute IOB Placement
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Design is not getting complied.

How should I resolve this issue.

 

Regards,

Vinayak Kumthekar

 

 

 

0 Kudos
2 Replies
pvenugo
Moderator
Moderator
5,117 Views
Registered: ‎07-31-2012

Hi,

 

Please refer to http://www.xilinx.com/support/answers/34635.html

 

Regards

Praveen


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
5,088 Views
Registered: ‎08-04-2016

Hi Praveen,

 

I have instantiated EDK module in my ISE top module.

If I reduce number if Input and Outputs or change to bigger FPGA device or if I comment all signals in UCF then also this error in occurring.


@pvenugo wrote:

Hi,

 

Please refer to http://www.xilinx.com/support/answers/34635.html

 

Regards

Praveen


 

Thanks,

Vinayak

 

0 Kudos