06-22-2016 12:50 PM
I am looking at how SPI from the MPSoC is wired out via EMIO, and it appears to be wired differently than the Zynq-7000 device before it.
If you create two designs, one with an MPSoC and one with Zynq-7000, for both wire SPI0 out via EMIO, and then generate the top level HDL wrapper, you will notice that instead of the more common MSIO and MOSI port names, the names on the HDL wrapper are SCLK, SS, IO0, and IO1.
For Zynq-7000 devices, the IO1 input signal is wired to EMIOSPI0MI (SPI 0, Master, MISO) on the PS7 IP block (you can view this via schematic from a synthesized design). For MPSoC designs, it appears that IO1 input is wired to EMIOSPI0SI (SPI 0, Slave, MOSI) on the PS8 IP block.
Can anyone from confirm this? Is this a bug?
12-20-2017 12:54 AM
I think I have the same problem in Vivado 2017.3. I have not checked the schematics but the symptoms are that SPI transfers seems to be internally loopbacked, read data = write data.
Also the signal renaming from IPI schematics to HDL is confusing. spi_emio_m* and spi_emio_s* becomes spi_io0* and spi_io1* with no obvious indication which is miso or mosi.
02-22-2018 04:36 AM - edited 02-22-2018 04:37 AM
Hi, Also in Vivado 2017.4 it seems MISO will not be connected to the PSU-SPI. I can see MISO comes from the pin when monitoring with System-ILA. But the PSU-MISO mirrors PSU-MOSI!
Remembering on the naming is not too complicated: SPI-Io0 means MOSI (m0si), SPI-Io1 means MISO (m1so).
02-22-2018 07:40 AM
EMIO SPI_0 under the signal do not have all use, you only need to use the following four signal lines can be (see below):
emio_spi0_m_i -> MISO
emio_spi0_sclk_o -> CLK
emio_spi0_ss_o_n -> SS
02-22-2018 08:31 AM
I will test it. Is there an official AR#? Normally when working with Interfaces Vivado should route them correctly. Please see my SR#10428503 and pelase check whether there has an CR# been filed.
07-02-2018 08:46 AM
It is still not clear to me how spi_0_io0 and spi_0_io1 in the HDL wrapper map to emio_spi0_m_o and emio_spi0_m_i in the block diagram. Can someone explain how this is mapped? Also, why are the signals in the HDL wrapper not matching the signals in the Vivado block diagram?
I am using a Zynq UltraScale+ MPSoC XCZU15EG-FFVB1156 in Vivado 2018.1