12-30-2014 01:00 AM
Hi, what i understand from TRM is that maximum supported SPI flash size is 16 MB. But with dual QSPI mode, it is possible to obtain 32 MB addressing area. My questions :
1) Is this 32 MB for both flash chips ? I mean it should be 16 MB + 16 MB right ?
2) http://www.xilinx.com/support/answers/50991.html In this link, Zynq supported configuration SPI flash chips are listed. 1024 Mb and 512 Mb Mb SPI flash chips are also included. I guess these are added considering software controlled IO mode. If i use for example, 32 MB + 32 MB dual parallel mode, does this mean boot code will execute from the lower 32 MB ?
12-31-2014 04:56 AM
OZOM REV A is assembled with 2 x 32MByte spansion, and YES to you question:
with dual parallel you have XiP linear space of 32MByte, this is the maximum in linear mode
beware that the FSBL checks for flash size > 16MB and completly disable linear mode if larger device is used, so small patch is needed to re-enable linera mode if wanted