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jagron
Adventurer
Adventurer
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Registered: ‎01-04-2008

MicroBlaze Synchronization Instructions

The new (11.4) MicroBlaze synchronization instructions LWX/SWX do not specify whether or not the resevation is accessible to external devices such as hardware accelerators and other processors.  The documentaiton says that the state is held internally (page 25 of mb_ref_guide.pdf), which leads me to believe that it can only be used for uni-processor synchronization.  The reference guide also mentions a new MSR coherence bit, but the current implementation does not yet support the coherence functionality.

 

Does anybody have any additional information on the subject?  Any info will be greatly appreciated.

 

Sincerely,

-Jason

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goran
Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

There is no way to do synchronization accesses over PLB or XCL so the current implementation only works internally to MicroBlaze.

The usage is for creating synchronization primitives like spinlock.

 

I don't know what coherence bit for MSR you are referring to and the only meantioning of the word "coherence" in the reference guide is for the MMU TLB information.

 

Göran

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