cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
922 Views
Registered: ‎06-06-2018

Microblaze - JESD204B

Jump to solution

Hello,

 

I am new to Xilinx Vivado. I am currently using Vivado 2014.2 version. I am currently working on a project which requires JESD204B interface along with Microblaze Soft Core Processor. I am trying to interface a DAC to Xilinx FPGA. I wonder if I am connecting the things correctly. I am using designer assistance available in vivado. My current task is to store the data samples in a memory and read out them to the DAC through JESD204B interface. I am uploading a picture of my block design. I would like to know whether the design is correct or not. Also, I am not able to edit the BRAM parameters. I want to store the data samples in BRAM so that I will be able to read them out to the JESD204B core. I would appreciate the help.

 

Regards,

 

Loukik Pingle

 

Untitled.png

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
1,050 Views
Registered: ‎09-12-2007

You design looks OK.

 

 I want to store the data samples in BRAM so that I will be able to read them out to the JESD204B core. I would appreciate the help.

 

I only see your LMB BRAM here. This will be used for your Microblaze applciation code, so I wouldnt place your data samples here. You should add an AXI BRAM Controller. You can use updatemem to populate the BRAM with your data samples via the MEM file. The tools will create the MMI file for you that updatemem will need to populate the BRAM (see chapter 7 here for more info on the updatemem). Then it is up to you on how you want to feed the JESD IP with the data samples, you can use a DMA, or you can do this manually in your application code. However, I would recommend the DMA. There is example DMA code in the drivers delivered with SDK that you can use as reference.

 

 

View solution in original post

2 Replies
Highlighted
Moderator
Moderator
1,051 Views
Registered: ‎09-12-2007

You design looks OK.

 

 I want to store the data samples in BRAM so that I will be able to read them out to the JESD204B core. I would appreciate the help.

 

I only see your LMB BRAM here. This will be used for your Microblaze applciation code, so I wouldnt place your data samples here. You should add an AXI BRAM Controller. You can use updatemem to populate the BRAM with your data samples via the MEM file. The tools will create the MMI file for you that updatemem will need to populate the BRAM (see chapter 7 here for more info on the updatemem). Then it is up to you on how you want to feed the JESD IP with the data samples, you can use a DMA, or you can do this manually in your application code. However, I would recommend the DMA. There is example DMA code in the drivers delivered with SDK that you can use as reference.

 

 

View solution in original post

Highlighted
Visitor
Visitor
837 Views
Registered: ‎06-06-2018

Thanks for letting me know. I am trying to do a basic design before making a jump to the Microblaze. I have implemented the following block design in Vivado. I am using a ROM to store the data samples and a counter attached to it. The ROM is reading out the data samples to the JESD204B IP core which is configured for 8 lanes per link. I am using the same configuration the other side i.e on the DAC. I am trying to interface Kintex-7 to AD9172 Dual link DAC, I just want to test the design hence I am going with this basic approach. Later, I plan to make the use of Microblaze Soft Core Processor and a BRAM. The problem now is I have implemented the design and have generated the bit file for it. I have programmed the FPGA and I have the AD9172 attached to the FMC connecter present on the board. I have configured the AD9172 for the same configuration i.e. 8 Lanes per link and in Subclass 1 mode. I have connected the signals as it appears in the figure and I am still not able to get the output on the DAC side. I am wondering whether I have made the right connections or am I missing some signals which are to be connected.

I would appreciate the help. 

 

Untitled.png

0 Kudos