Im developing a basic SoC for processing some data in software. Basically the SoC will analyze images stored in the DDR. Currently, I'm using an Arty A7-100T for the prototype, and with the MIG controller for the DDR the maximum output clk frequency is 83.33MHz, due to the FPGA speed grade.
I know the maximum frequency for the Microblaze is dependent of the elements like the Instrucction Cache, Data Cache... (I only use Basic FPU and 32 bit Multiplier)
So my first solution was to double the clocks, one clock wizard with 240MHz for the Microblaze and the AXI Buses and Peripherals, and another clock for the MIG (166.667MHz for sys_clk and 200MHz for ref_clk, as it is recomended).
The timing failed, but Vivado has generated the bitstream. But the program it is as slow as before, no matter what clock I'm using (83.33MHz or 240MHz). So, I would like to know if there is any other option to implement, the Microblaze with a faster clock, because the maximum speed I can get from the MIG is 83.33MHz and with another clock driving the processor, it looks like it is running at the same speed.