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deepikadasari31
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Participant
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Registered: ‎05-30-2019

Missing of Data in Last Buffer Descriptor while using AXI DMA, SG Cyclic mode

Hi Team,

First we tried in DMA Simple register mode due to more latency between the transfers , we moved to SG mode. We are sending continuous data for every 100 microseconds from PL to DMA(PS side). We modified the example code of dma sg poll provided by xilinx. In this we enabled the cyclic mode to reuse the Buffer Descriptors(BD) for receiving the continuous data into BD's.

Initially we will send two transfers(2) and then for every 100us we send three continuous data transfers(3,3,3....). We are able to receive 2+3 =5 transfer data correctly but while sending next three data transfers the data is missing in One of the BD's. We are attaching the code for your reference. Please help us to solve this problem.

NOTE: We are checking the data in the Receiving Side of DMA(S2MM).

For Example:

Let 1st data : 0x1111111

2nd data: 0x2222222,

3rd data : 0x3333333, 4th data : 0x4444444, 5th data : 0x5555555,

Now for every 100us 3rd to 5th data is repeated i.e.

3rd data : 0x3333333, 4th data : 0x4444444, 5th data : 0x5555555,

3rd data : 0x3333333, 4th data : 0x4444444, 5th data : 0x5555555,...

 

Result:

First 5 transfers,

1st data : 0x1111111

2nd data: 0x2222222

3rd data : 0x3333333,

4th data : 0x4444444,

5th data : 0x5555555,

For the second repetition of 3 data transfers,

3rd data : 0x0, 4th data : 0x4444444, 5th data : 0x5555555,

3rd data : 0x0, 4th data : 0x4444444, 5th data : 0x5555555,...

 

Thanks in advance,

Deepika.

 

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