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More Vivado AXI Interconnect "tricell" errors

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I had previously run into these AXI interconnect tricell errors, and worked around them here.  I then added an additional external DMA interface to my design (for network DMA reads), and the tricell errors reappeared (during synthesis):

 

[Project 1-486] Could not resolve non-primitive black box cell 'tricell' instantiated as 'xbar_i_32' ["..../sources_1/bd/cpu/hdl/cpu.vhd":1378]

I'm running Vivado 2013.2 under Win 7 x64.  This is still a Microblaze+DDR3 design, with some additional custom AXI interfaces.  As before, it looks like something is going wrong with the block design's autogenerated AXI interconnect.  Has anyone else seen these errors, have some clues about how to find the source of the errors, or know of a solution?  From this and my previous experience, it seems like the BD AXI interconnect generation just fails at a certain level of complexity.  Previously, I was able to correct these errors by making the AXI buses smaller (64 instead of 256 bits), or simpler (write-only instead of read-write).

 

Thanks in advance for any suggestions!

 

-Greg

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Registered: ‎02-27-2008

Re: More Vivado AXI Interconnect "tricell" errors

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A summary of problems and solutions in working through my ISE to Vivado migration:

 

- Tricell errors: Moving from Vivado 2013.2 to 2013.3 fixed these.

- FSL errors: My design depends on an FSL write happening before an FSL read.  Something somewhere changed between ISE 14.6 and Vivado 2013.3.  I used to do 2 FSL writes to guarantee it went through before a write, now I have to do 3 writes.

- Debug core errors:  I still cannot use the simple approach of using MARK_DEBUG on nets and then automatically generating an ILA core (same invalid file name errors).  The simple approach does work on a small project.  However, instantiating an ILA core from the IP library and hooking up nets to the probes explicitly works.

- Debug communication errors: Once I got my design to compile with an ILA in it, debugging it from the Vivado IDE failed with a variety of vcse type errors, until I removed a custom core in my design that was using a different USERCHAIN.  Shouldn't make a difference, but does.  Maybe the debugger is probing every USERCHAIN and chokes when it talks to mine?

- DMA errors: One of my custom DMA cores was obliterating memory when a DMA started.  After lots of experimentation, I discovered that the Vivado MIG core had shrunk its address space from 2GB to 512MB, even though its settings are identical to the ISE 14.6 MIG that worked.  Hand editing the MIG project file (which it tells you explicitly not to do) restored normal operation.

 

Normally I'd file a webcase to report these Vivado bugs and get them squashed, but that's no longer an option, so this forum entry is it.  Good luck!

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Registered: ‎02-27-2008

Re: More Vivado AXI Interconnect "tricell" errors

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Related warnings from synthesis before the critical error include:

 

WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S01_AXI_awready_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S01_AXI_bid_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S01_AXI_bresp_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S01_AXI_bvalid_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S01_AXI_rid_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S01_AXI_wready_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S03_AXI_awready_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S03_AXI_bid_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S03_AXI_bresp_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S03_AXI_bvalid_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S03_AXI_rid_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/S03_AXI_wready_INST_0 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_1 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_10 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_11 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_12 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_13 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_14 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_15 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_16 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_17 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_18 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_19 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_2 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_20 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_21 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_22 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_23 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_24 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_25 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_26 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_27 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_28 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_29 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_3 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_30 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_31 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_32 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_4 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_5 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_6 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_7 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_8 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.
WARNING: [Opt 31-31] Blackbox mbcpu/axi_interconnect_1/xbar_i_9 (tricell) is not supported or not found. This blackbox cannot be found in the existing library.

 Why the tools are trying to implement 3-state logic for the unused AXI write channels of the read-only Microblaze instruction port (S01) and my read-only DMA channel (S03) is a mystery.

 

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Re: More Vivado AXI Interconnect "tricell" errors

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I moved my project from Vivado 2013.2 to 2013.3.  The tricell errors have gone away, but the Microblaze processor now hangs on FSL instructions.  In addition, when I try to add a debug core to watch the FSL signals in Vivado, implementation fails saying:

 

opt_design failed
Implementing debug core u_ila_0 failed.
ERROR: [Chipscope 16-133] Failed to generate and synthesize debug IP "xilinx.com:ip:ila:3.0".
ERROR: [Ipptcl 7-5] XIT evaluation error: Invalid file name: c:/Users/testjuser/AppData/Local/Temp/u_ila_0_CV_2-5848/u_ila_0_CV.srcs/sources_1/ip/u_ila_0_CV/u_ila_0_CV_ooc.xdc
ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-1710] Problem delivering 'Synthesis' files for IP 'u_ila_0_CV'.
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.

The battle continues...

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Re: More Vivado AXI Interconnect "tricell" errors

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A summary of problems and solutions in working through my ISE to Vivado migration:

 

- Tricell errors: Moving from Vivado 2013.2 to 2013.3 fixed these.

- FSL errors: My design depends on an FSL write happening before an FSL read.  Something somewhere changed between ISE 14.6 and Vivado 2013.3.  I used to do 2 FSL writes to guarantee it went through before a write, now I have to do 3 writes.

- Debug core errors:  I still cannot use the simple approach of using MARK_DEBUG on nets and then automatically generating an ILA core (same invalid file name errors).  The simple approach does work on a small project.  However, instantiating an ILA core from the IP library and hooking up nets to the probes explicitly works.

- Debug communication errors: Once I got my design to compile with an ILA in it, debugging it from the Vivado IDE failed with a variety of vcse type errors, until I removed a custom core in my design that was using a different USERCHAIN.  Shouldn't make a difference, but does.  Maybe the debugger is probing every USERCHAIN and chokes when it talks to mine?

- DMA errors: One of my custom DMA cores was obliterating memory when a DMA started.  After lots of experimentation, I discovered that the Vivado MIG core had shrunk its address space from 2GB to 512MB, even though its settings are identical to the ISE 14.6 MIG that worked.  Hand editing the MIG project file (which it tells you explicitly not to do) restored normal operation.

 

Normally I'd file a webcase to report these Vivado bugs and get them squashed, but that's no longer an option, so this forum entry is it.  Good luck!

View solution in original post

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