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jstrubleboeing
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Registered: ‎05-28-2019

Native Control of AXI4-Lite Master

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Folks, I'm really confused on what must be a very simple problem.  I have a decent size FPGA (Artix-7 200) on a custom board.  There is no CPU, PCIe link, or any other interface other than a simple (and custom) 3-wire serial IO link from a much larger device on a COTS board.  Many of the modern cores expect an AXI4 interface (fine by me) but I don't have one handy.

So is there a simple core that will let me generate an AXI4-Lite cycle to query an AXI endpoint that lacks a native interface? 

The simplest example is the XADC core.  I want to read the temperature of FPGA.  But this is a good example because it lacks a native interface (as far as I can tell) other than the alarm outputs.  So what would be the right approach to come from my native VHDL to get the temperature data?  I believe that would address my larger problem as well.

Much thanks in advance,

 

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dgisselq
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Registered: ‎05-21-2015

@florentw,

Microblaze is simple?  Seriously?  Even a small microblaze requires a memory (block RAM perhaps), start up instructions (i.e. flash+flash controller), and a complex AXI interconnect.  That's several thousand LUTs right there, before you get to any specific application code.  To make matters worse, a CPU tends to be a big black box to a designer, making debugging all the more difficult.

This is not what I would recommend for a simple solution.

@jstrubleboeing,

If you just want a simple interface, I'd recommend one of two approaches.  1) For the simplest, build your own AXI-lite controller to speak to the device directly.  It doesn't get easier than that.  If it helps, you can find a formal verification property set on-line to know you've got your design right.  2) If AXI-lite is still too difficult, then consider using a simpler bus structure, something like Wishbone perhaps.  You can then bridge from WB directly to AXI-lite.  As long as there are no other peripherals for your master to select between, no need to change data widths, no need to change clock domains, etc., this should be pretty simple for you.

Dan

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florentw
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Registered: ‎11-09-2015

HI @jstrubleboeing ,

You might want ot look for implementing a small microblaze. This would be the easiest way.

Another IP you could look at is the AXI traffic generator.

Or last option: if you create a new custom IP with AXI4-Lite interface, the tool will create a VHDL/Verilog template for you. You could use it for your custom logic.

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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dgisselq
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Registered: ‎05-21-2015

@florentw,

Microblaze is simple?  Seriously?  Even a small microblaze requires a memory (block RAM perhaps), start up instructions (i.e. flash+flash controller), and a complex AXI interconnect.  That's several thousand LUTs right there, before you get to any specific application code.  To make matters worse, a CPU tends to be a big black box to a designer, making debugging all the more difficult.

This is not what I would recommend for a simple solution.

@jstrubleboeing,

If you just want a simple interface, I'd recommend one of two approaches.  1) For the simplest, build your own AXI-lite controller to speak to the device directly.  It doesn't get easier than that.  If it helps, you can find a formal verification property set on-line to know you've got your design right.  2) If AXI-lite is still too difficult, then consider using a simpler bus structure, something like Wishbone perhaps.  You can then bridge from WB directly to AXI-lite.  As long as there are no other peripherals for your master to select between, no need to change data widths, no need to change clock domains, etc., this should be pretty simple for you.

Dan

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florentw
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Registered: ‎11-09-2015

@dgisselq wrote:

@florentw,

Microblaze is simple?  Seriously?  Even a small microblaze requires a memory (block RAM perhaps), start up instructions (i.e. flash+flash controller), and a complex AXI interconnect.  That's several thousand LUTs right there, before you get to any specific application code.  To make matters worse, a CPU tends to be a big black box to a designer, making debugging all the more difficult.

This is not what I would recommend for a simple solution.

[Florent] - I said simple not small ;)

You do not need to take care of the RTL. I see that as simple


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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jstrubleboeing
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Registered: ‎05-28-2019

OK, so building a simple AXI-Lite controller sounds like the way to go here.  I had hooked up things using AXI but never considered trying to generate the traffic as it simply looked to complex.  But the link you provided sounds quite promising.  I should be able to do something simple as described.

Thanks for the prompt response(s).

 

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johnmcd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

Or use the jtag axi master IP. Then you can use scripting in Hardware Manager to read/write from peripherals.

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