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toddmcc
Adventurer
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Registered: ‎09-01-2015

No INTR in xparameters.h

Hey all, I am trying to connect a level generated irq from a custom IP block to a Zynq processing system 7 block. I can make the connection, build it and see that the bd.tcl file has connected the blocks correctly. However when I export it to SDK and run a BSP the xparameters.h does not show the INTR it should have in there. We had this working a few weeks ago and there have been a few changes but nothing at the top level where this would be affected so I can't understand why it is not seeing this connection now. I can also take an AXI timer and connect it to a concat block and run both the timer and the custom IRQ to the Zynq PS and the xparameters.h will actually show the AXI IRQ connection but not the one from the custom IP. A colleague says that the custom IP has to have an AXI interface on it for the IRQ to be recognized but I cannot find any documentation as to this restriction nor see why this would make sense? I have seen some other posts regarding this issue but there have been no solutions. Anybody seen or know of this issue?
irq_connected.jpg
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toddmcc
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Registered: ‎09-01-2015

Really!? No one has had or seen this problem in 2015.4? Must be another fine Vivado "feature".
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lbyoopp
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Registered: ‎02-08-2015

Hi, for the late reply.

 

We have exactly the same problem.

 

We connect 6 INTR to IRQ_F2P, and only AXI TIMER0, AXI TIMER1, MM2S INTR and S2MM INTR are generated, the rest two generated by my custom IP, INTR0 and INTR1 are not generated in xparameters.h.

 

I am using Vivado 2017.1

a.png
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lbyoopp
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Registered: ‎02-08-2015

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stephenm
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Registered: ‎09-12-2007

Yes, as you have already discovered. The BSP TCL read all pins wiht type Interrupt. So, if you have a custom IP with an interrupt then make sure the pin type is set accordingly.

 

This would be the same for the devicetree generator in linux

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lbyoopp
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Registered: ‎02-08-2015

But, can these pins be back referenced?

 

For example, If the signal(5:0) are connected to F2P intr port, then the initial design would be assumed that these pins are INTERRUPT, without additional (unnecessary) settings.

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