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dileepkumu
Observer
Observer
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Registered: ‎07-19-2018

PL DDR memory access for PS using DMA

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I am working on a project to access the PL DDR4 memory from the PS. I was able to connect the DDR4 MIG IP to the AXI interconnect and connect the AXI interconnect to the MPSOC. We are able to read and write from the PL DDR. I would like to add a DMA to speed up the data transfer between PL DDR and PS. How can I do it?

Thanks

Dileep

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katsuki
Xilinx Employee
Xilinx Employee
681 Views
Registered: ‎11-05-2019

Hi @dileepkumu 

Did you assign the address segment correctly? It is better to make a simple design and try it. For example,

bd.PNG

ad.PNG


In your block design, Port C0_DDR4_S_AXI_CTRL is the port for MiG Configuration, do you need to use this port? The following posts may also be helpful.
Memory Address Overlap Error with PL-Side DDR4


Thank you.
Don't forget to Reply, Kudo, and Accept as Solution.


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patocarr
Teacher
Teacher
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Registered: ‎01-28-2008

Hi @dileepkumu 

  If using standalone libraries, you can use the PS ZynqMP DMA driver.

Thanks,

-Pat

 

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https://tuxengineering.com/blog

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dileepkumu
Observer
Observer
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Registered: ‎07-19-2018

Hi @patocarr ,

Thanks for the reply. But I wanted to know how you connect the DMA IP in the block design.

Thanks

Dileep

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katsuki
Xilinx Employee
Xilinx Employee
735 Views
Registered: ‎11-05-2019

Hi @dileepkumu 

The ZynqMP DMA proposed by @patocarr is a DMA in PS, so there is no need IP. It depends on your requirements, for an example of using DMA IP for PL, the following blog will be helpful.

AXI CDMA Linux user space example on Zynq UltraScale+ RFSoC

Thank you.
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dileepkumu
Observer
Observer
699 Views
Registered: ‎07-19-2018

Hi @katsuki,

Thanks for your reply. I have tried to connect the CDMA IP according to the example you have mentioned but I ran into an issue when I tried to validate the design. I have attached the block design and the error messages.

The error message says that Slave segment </ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK> is mapped into master segment </zynq_ultra_ps_e_0/Data/SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK> but there is no path between them.

Thanks

Dileep

CDMA_DDR.JPG
CDMA_Error.JPG
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katsuki
Xilinx Employee
Xilinx Employee
682 Views
Registered: ‎11-05-2019

Hi @dileepkumu 

Did you assign the address segment correctly? It is better to make a simple design and try it. For example,

bd.PNG

ad.PNG


In your block design, Port C0_DDR4_S_AXI_CTRL is the port for MiG Configuration, do you need to use this port? The following posts may also be helpful.
Memory Address Overlap Error with PL-Side DDR4


Thank you.
Don't forget to Reply, Kudo, and Accept as Solution.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

View solution in original post

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katsuki
Xilinx Employee
Xilinx Employee
604 Views
Registered: ‎11-05-2019

Hi @dileepkumu 

Is there any update? If you have any questions, you can post them.
If already issue has resolved, give Kudo, and mark Accept as Solution to close this post.

Thank you.
Don't forget to Reply, give Kudo, and mark Accept as Solution.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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vanmierlo
Mentor
Mentor
558 Views
Registered: ‎06-10-2008

@dileepkumu 

What do you intend to do? Your current design enables the DMA engine to move the random power up values around in the DDR4 RAM. But nothing else can access it.

C0_DDR4_S_AXI_CTRL is only for configuring the MIG.

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