I want to share data between PS and PL using DDR4 ram, data is in the form of Matrixes and I am using ZCU104 board.
1-The data will be initiated in the DDR4 by the ARM,
2- A controller is implemeted in the PL side,which is also being controlled by ARM using Axi-Lite , this controller needs to read this initated data, perform computations and also write its output back (also in the form of matrix) to the DDR4.
3- ARM reads the controller output from memory, based on the output writes new data to DDR4 and agian starts controller to perform computation.
I am facing problem in sharing the data between PS and PL, what are the possible options which I can use to share this data between PL and PS.
Controller have been implemented using VIVADO HLS and I am using block design function of Vivado Hlx and Xilinx SDK for the complete implementation.
I am new to XIlinx and FPGS so Can anyboday point me to possible design example of similar kind.