Is there a design example available in Vivado for PL-PS data movement using DMA. I am using a ZC106 board, and need a mechanism to transfer high-throughput data in both directions (PL to PS and PS to PL). Conceptually, I know I can use the AXI HP ports on the PS-PL interface, but wanted to know if there is an example design I can use as a starting point.
Along similar lines, is there any advantage in using on-chip BRAM in PL vs a DDR4 hanging off the PL for shared memory data transfer? I would think using an on-chip BRAM would be faster than using external DDR4 but wanted to confirm