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Contributor
Contributor
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Registered: ‎08-25-2014

PL<-->DDRC Latency

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Are there some published numbers on the PL<-->DDRC latency?  I'm specifically interested in worst-case read latency numbers for random access (ignoring the DDR latency numbers--these can be accounted for) for each of the ports.  From what I've read on these boards and in the documentation, the ACP has the lowest average latency, but can suffer from occasional long latency reads depending upon cache misses.  And the HPx ports have the highest throughput and are optimized for bursts, but has a longer average latency.

 

For our purposes, we need a latency of no more than about 600ns.  With DDR3-1066 (actually operating at 525MHz, so call it DDR3-1050), what would be the worst case read latency from the PL to the memory, with say 7-7-7-21.  It seems that even with these timing parameters, the DDR3 memory itself isn't a bottleneck.  But if the PL is at say 125MHz and the PS has pclk at 50MHz (so the DDR controller is a 525MHz), what is the latency through the interconnect and controller?

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Scholar
Scholar
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Registered: ‎09-05-2011
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Scholar
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Registered: ‎09-05-2011
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Contributor
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Registered: ‎08-25-2014

sampatd, thanks for the link!

 

I'm already going down the path after finding the AXI Performance Monitor IP.  But the document you linked has lots of good stuff.

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Advisor
Advisor
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Registered: ‎10-10-2014

@pladow6262 @sampatd  I was looking for an answer to your question too ... but I'm wondering if a refresh isn't far worse than the latency ... from a PL point of view, you have no idea when a refresh will occur. I'm not a DDR expert, but doesn't a refresh result in the DDR being unaccessible during many cycles?

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