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Visitor
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Registered: ‎11-19-2019

PL to PS Interrupt on Zynq ultrascale+ using custom IP on the PL side

Hi,

Im new to Zynq and seem to be having some issues recieving and interrupt from a custom IP that is connected to the PS_PL_IRQ pin in the vivado design. 

I have several questions:

1) do i need to manually enable the interupt by writing the adress offset of the config registers in the AXI memory location?

2)I generated the code below from examples and tutorials im i missing something?

 

// Parameter definitions
#define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
#define PLTOPS_DEVICE_ID
#define INTC_DEVICE_INTERRUPT_ID XPAR_FABRIC_AXI_INTC_0_IRQ_INTR

static int IntcInitFunction(u16 DeviceId)
{

XScuGic_Config *IntcConfig;
int status;

Xil_ExceptionInit();

// Interrupt controller initialization
IntcConfig = XScuGic_LookupConfig(DeviceId);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
status = XScuGic_CfgInitialize(&INTCInst, IntcConfig, IntcConfig->CpuBaseAddress);
if(status != XST_SUCCESS)
return XST_FAILURE;

XScuGic_SetPriorityTriggerType(&INTCInst, INTC_DEVICE_INTERRUPT_ID, 0, 0x3);

status = XScuGic_Connect(&INTCInst, INTC_DEVICE_INTERRUPT_ID, (Xil_ExceptionHandler)Data_Rdy_Intr_Handler, (void *)&INTCInst);
if(status != XST_SUCCESS)
return XST_FAILURE;

XScuGic_Enable(&INTCInst, INTC_DEVICE_INTERRUPT_ID);
xil_printf("Enabled IRQ id:%d\n\r", INTC_DEVICE_INTERRUPT_ID);

Xil_ExceptionInit();

Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &INTCInst);

Xil_ExceptionEnable();

return XST_SUCCESS;
}

 

void Data_Rdy_Intr_Handler(void *InstancePtr)
{

    printf("interupt\n");

}

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Visitor
Visitor
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Registered: ‎11-19-2019

Re: PL to PS Interrupt on Zynq ultrascale+ using custom IP on the PL side

I have been doing more digging and found examples for an intc controller which seems to not use the GIC. 

1) Is the GIC only for controlling the axi interrupt controller interrupts and intc for PS_PL_IRQ interrupts?

2) can some one clarify what i should use for an interrupt from a custom ip to the PL_PS_IRQ0 on the Zynq ultrascale+

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Moderator
Moderator
445 Views
Registered: ‎07-31-2012

Re: PL to PS Interrupt on Zynq ultrascale+ using custom IP on the PL side

Hi @boris.khasin ,

Please make sure that you are seeing the custom IP's interrupt ID# in xparameter.h prior to testing in application.

If not, then custom IP interrupt port is not set as intr in properties. 

GIC is PS interrupt controller capable of taking to PL interrupt controller i.e. AXI INTC and peripheral irq routed to it directly.

 

Regards

Praveen

 


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Highlighted
Visitor
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Registered: ‎11-19-2019

Re: PL to PS Interrupt on Zynq ultrascale+ using custom IP on the PL side

Thank you for the response. The Xparameter.h shows:

/* Shared Peripheral Interrupts (SPI) */
#define XPS_FPGA0_INT_ID 121U
#define XPS_FPGA1_INT_ID 122U
#define XPS_FPGA2_INT_ID 123U
#define XPS_FPGA3_INT_ID 124U
#define XPS_FPGA4_INT_ID 125U
#define XPS_FPGA5_INT_ID 126U
#define XPS_FPGA6_INT_ID 127U
#define XPS_FPGA7_INT_ID 128U
#define XPS_FPGA8_INT_ID 136U
#define XPS_FPGA9_INT_ID 137U
#define XPS_FPGA10_INT_ID 138U
#define XPS_FPGA11_INT_ID 139U
#define XPS_FPGA12_INT_ID 140U
#define XPS_FPGA13_INT_ID 141U
#define XPS_FPGA14_INT_ID 142U
#define XPS_FPGA15_INT_ID 143U

Are these no the ones.

Boris

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Moderator
Moderator
328 Views
Registered: ‎07-31-2012

Re: PL to PS Interrupt on Zynq ultrascale+ using custom IP on the PL side

Hi @boris.khasin ,

The interrupt IDs looks fine in xparameter.h file.

Conceptually, you will get idea of PL to PS interrupt from https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-38-Answering-a-question/ba-p/479978

 AR: http://www.xilinx.com/support/answers/60837.html -- shows how to create a custom AXI IP with Interrupt enable and how to use it and verify using SDK
AR: http://www.xilinx.com/support/answers/50572.html -- Generic example for PL based interrupt but using AXI Timer.
I hope the second link would help you.

 

Regards

Praveen


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