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stanr
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11,830 Views
Registered: ‎02-12-2010

PL to PS Interrupts on MPSoc Zynq

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I have 5 interrupts from the PL fabric that I need to bring into the PS. What is the best method to do that? Should I use direct connect to the GIC? Also need a Bare Metal SDK example on how to use these IRQ's. I have not seen any examples on how to do this.

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stanr
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Registered: ‎02-12-2010

I have the IRQ port on the BD, that is not the problem. I have a AXI Timer IRQ working, no issues there. It just is with the PL IRQ's that I have. It has been confirmed by the support team that there does seem to be an issue that they are going to try and fix in the 2016.3 release. Thanks for the reply.

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muzaffer
Teacher
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Registered: ‎03-31-2012
In PS7 IP configuration dialog enable the PL->PS interrupts and connect your interrupts to the port exported from PS7 block.
There are many examples of connecting interrupts in bare-metal designs. Search for uart etc.
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stanr
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Registered: ‎02-12-2010

Thanks for the reply!!

We have done PS7 designs, but the new Zynq UltraScale parts seem like they handle interrupts differently. There is no dialog for the PL to PS connections as there was in the PS7. I have done an exhaustive search and really have not found much on this topic.

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muzaffer
Teacher
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Registered: ‎03-31-2012

@stanr I just created a sample project with 2016.2 for a zu3eg chip. When I double click on the Zynq block in the BD editor, I get this dialog which lists PS-PL configuration on the left. Interrupts are on PS-PL configuration, General, Interrupts, PL to PS section. When I select that I get a pl_ps_irq port on the Zynq block.

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stanr
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Registered: ‎02-12-2010

I have the IRQ port on the BD, that is not the problem. I have a AXI Timer IRQ working, no issues there. It just is with the PL IRQ's that I have. It has been confirmed by the support team that there does seem to be an issue that they are going to try and fix in the 2016.3 release. Thanks for the reply.

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sadhvisalaka
Contributor
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Registered: ‎04-21-2017
HI @stanr

DID u got the solution for ur problem?
I am also doing the same PL O PS interrup. can u please help me

with regards sadvi
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ferrytale
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Registered: ‎04-03-2014

I am using Vivado 2017.4 having trouble with connecting 2 interrupts (from vdma) to PL to PS Interrupt port of the ultrascale+

The pl_ps_irq0 port width is not adapting. Block design validation shows no errors, but when i start synthesis, it warns me because of the port width mismatch.

 

ultrascale_irq_problem.jpg

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pvenugo
Moderator
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7,689 Views
Registered: ‎07-31-2012

Hi @ferrytale,

 

Did you validate the block design to update port widths before going for synthesis?

This is required to update the block design changes.

Were you able to re-instantiate Zynq US+ IP in block design and see this issue?

Regards

Praveen


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pvenugo
Moderator
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7,569 Views
Registered: ‎07-31-2012

Hi,

 

Please share the bd tcl file replicate the issue as at our end this behavior is not seen.

 

Regards
Praveen


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thelarys
Newbie
Newbie
6,397 Views
Registered: ‎07-01-2018

Ferrytale, did you get this resolved? I am seeing the exact same issue. I have two interrupts concat together and passed into pl_ps_irq0. The properties of the bd_pin show a width of 2, but the range is still 0:0, so it won't work.

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anjaneyulu.challa9
Adventurer
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5,765 Views
Registered: ‎04-11-2017

Have you tried regenerating the bd wrapper file which connects the block design to the PL logic ?

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thelarys
Newbie
Newbie
5,754 Views
Registered: ‎07-01-2018

Thanks to @Praveen for the solution to this.  I deleted the zynq IP and re-instantiated it.  Solved the problem.

jrp
Explorer
Explorer
4,079 Views
Registered: ‎01-24-2018

Really... deleting the MPSOC IP block fixes it?

What a joke!!!

HaHa

 

Fix your tools please!

 

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pvenugo
Moderator
Moderator
4,062 Views
Registered: ‎07-31-2012

Hi @jrp ,

Please provide your failed testcase with version used so that I recreate this issue and file request to fix the tool if seen in 2018.3 or later version.

Regards

Praveen


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