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ldm.eth
Explorer
Explorer
673 Views
Registered: ‎01-15-2019

PL2PS Interrupts & HDF file

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Hi All,

Is it possible to understand from HDF file what inrerrupts are connected to Zynq? Especially PL2PS interrupts...

What files should FPGA Designer pass to Embedded Engineer, which should include such of info?

Thank you!

 

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abhinayp
Xilinx Employee
Xilinx Employee
640 Views
Registered: ‎07-12-2018

Hi @ldm.eth

 

You can view the hardware platform specification of the hardware system by double-clicking the HDF/ XML file under the hardware platform project in the Project Explorer view. SDK opens the hardware platform specification viewer, displaying the following overview information about the hardware design:

- Design information

- A list pf processors in the design, the processor memory map, and the list of peripherals in the processor sub-system 

- A list of IP blocks present in the design.

Best Regards
Abhinay PS
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abhinayp
Xilinx Employee
Xilinx Employee
641 Views
Registered: ‎07-12-2018

Hi @ldm.eth

 

You can view the hardware platform specification of the hardware system by double-clicking the HDF/ XML file under the hardware platform project in the Project Explorer view. SDK opens the hardware platform specification viewer, displaying the following overview information about the hardware design:

- Design information

- A list pf processors in the design, the processor memory map, and the list of peripherals in the processor sub-system 

- A list of IP blocks present in the design.

Best Regards
Abhinay PS
------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------

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ldm.eth
Explorer
Explorer
608 Views
Registered: ‎01-15-2019

How can I re-rout the PL interrupts from IRQ Core#0 pin to IRQ Core#1 pin of Zynq? Currently just IRQ for Core#0 is shown in the Zynq instance in the Block Design...

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stephenm
Xilinx Employee
Xilinx Employee
598 Views
Registered: ‎09-12-2007

with respect to viewing the HW, you can use the HSI API to open the HDF and you can view the cells, and nets that make up your HW here:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841693/HSI+debugging+and+optimization+techniques

 

If you make any changes to your HW, then you would need to do this in the Vivado IPI, and re-export to SDK to recreate the HDF file