09-20-2013 05:54 AM
I've recently managed with the help of Xilinx Support Engineer to build an ISE project that contains an EDK project consisting of XPS UART Lite only.
UART PLB interface is made external which is then connected to a module in ISE that in turn controls the XPS UART Lite IP Core. Note that the frequency expected by the IP Core is 100 MHz which matches the System Clock in Virtex-5 Mini Module Plus (XC5VFX70T).
I've done the following before writing this post:
- Read XPS UART Lite Data-Sheet
- Read IBM 128-Bit Processor Local Bus Architectural Specification (v4.6)
- Searched through forums.xilinx.com
- PLB interface is not responsive. Trying to read the Status internal register of XPS UART Lite using the PLB Non-Address Pipelining Read Transfer as explained in the specification. After setting the corresponding PLB ports no response is detected using ChipScope with depth of 16384.
- Design consists of two submodules that are directly connected, IP Core & User Logic.
- I've carefully checked net names in UCF file ... They match
- I'm using ISE 14.6
- In the attachment you can find the Translation Messages.
Any feedback is appreciated.
09-21-2013 06:24 PM
This seems to be a lot of work just to add a UART to a non-MicroBlaze project. I would think writing your own UART would be simpler than dealing with PLB. There is also a UART available for the PicoBlaze which is much easier to hook up to your HDL without a processor.
If you really want to use the UART from the EDK, I'd start looking at the address decoding to make sure that the UART is detecting accesses (there must be some sort of "chip select" decoding.
09-23-2013 01:59 AM
Thanks for your feedback.
Using EDK, I've access only to two Processor Types, PowerPC and MicroBlaze (PicoBlaze isn't available).
As for UART, I've already written my own VHDL module and its tested and working.
The main objective behind my current attempt is to use an EDK PLB IP Core in ISE without a processor. This attempt was already tried and solved for AXI in Xilinx Answer AR# 37856.
I'm using XPS UART Lite, because it's a simple IP Core where the PLB (v4.6) interface isn't used by its entirety (see figure below), thus easier to handle as a first attempt into using EDK PLB IP Core in ISE without a processor. Note that the marked signals aren't used in the XPS UART Lite PLB Bus Interface and according to EDK this IP Core is connected to a PLB v4.6 Bus interface in a regular MicroBlaze project.
The target result is to use the USB 2.0 Peripheral IP Core which is compatible with ULPI interface instead of developing one from scratch or adding an NXP Semiconductor Controller Chip which then has a Generic Processor Bus interface (This requires ~ 2 months).