04-01-2019 11:39 PM
Hello all,
I am working on ZYNQ ultrascale+(ZCU106) eval board.
1) What are the IPcore for PS to deal with 1G ethrnet using 1000BASE-X?
2) I want to get indepth of IPcore available with PS side(specifically for ethernet and PCIe), which document should i follow.
3) Whether PCS/PMA is acessible in PS side?
4) I want to send the data from a53 to R5 to PL using ethernet, How a53 will communicate R5?
Thanks
04-17-2019 09:16 AM
Hi @vikaskanha ,
1) What are the IPcore for PS to deal with 1G ethrnet using 1000BASE-X?
PS have GEM controller and if you want to use the PL side use AXI Ethernet subsystem.
2) I want to get indepth of IPcore available with PS side(specifically for ethernet and PCIe), which document should i follow.
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841791/Zynq+UltraScale+MPSoC+PCIe
3) Whether PCS/PMA is acessible in PS side?
4) I want to send the data from a53 to R5 to PL using ethernet, How a53 will communicate R5?
Yes, Inter process communication
Best Regards,
Srikanth