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vikaskanha
Contributor
Contributor
435 Views
Registered: ‎10-24-2018

PS IP CORE

Hello all,

I am working on ZYNQ ultrascale+(ZCU106) eval board.

1) What are the IPcore for PS to deal with 1G ethrnet using 1000BASE-X?

2) I want to get indepth of IPcore available with PS side(specifically for ethernet and PCIe),        which document should i follow.

3) Whether PCS/PMA is acessible in PS side?

4) I want to send the data from a53 to R5 to PL using ethernet, How a53 will communicate R5?

Thanks

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savula
Moderator
Moderator
373 Views
Registered: ‎10-30-2017

Hi @vikaskanha ,

1) What are the IPcore for PS to deal with 1G ethrnet using 1000BASE-X?

PS have GEM controller and if you want to use the PL side use AXI Ethernet subsystem.

2) I want to get indepth of IPcore available with PS side(specifically for ethernet and PCIe),        which document should i follow.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841791/Zynq+UltraScale+MPSoC+PCIe

https://www.xilinx.com/support/documentation/application_notes/xapp1305-ps-pl-based-ethernet-solution.pdf

3) Whether PCS/PMA is acessible in PS side?

https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_0/pg047-gig-eth-pcs-pma.pdf

4) I want to send the data from a53 to R5 to PL using ethernet, How a53 will communicate R5?

Yes, Inter process communication 

 

Best Regards,

Srikanth