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imuguruza
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Registered: ‎03-22-2017

Package delay: trace length implication

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Hi there,

 

I was just doing some numbers about the inner delays the xc7z020clg484-1 has in the DDR controller, and I'm quite puzzled with the results I have.

 

Taken the delay from Vivado, calculating mean delays in each pin and applying rule of thumb of 6.5ps/mm in FR4 material, the spreadsheet is showing that I must increase the length in 12.5mm of the signal that has the minimum delay (DDR A2) comparing to the length of the one that has the maximum delay (DDR CKE).

 

I dismissed the signal DDR Reset, because is not a requirement to length match as tight as other signals.

 

The difference is much bigger I expected, 12.5mm is quite a lot, specially if you have small boards and little space for routing...

Can someone confirm that these numbers are correct? 

 

Find attached the spreadsheet with calcs, in case someone wants to have a look on it.

 

BTW, I have read these forum entries as guidelines:

 

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Package-pin-delay-considerations-for-Zynq-PS-DDR3-PCB-routing/m-p/495444/highlight/true#M3038

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-PS-DDR-Delay-and-Trace-Matching-Question/m-p/526257/highlight/true#M3873

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Request-on-package-wire-length-table-for-all-i-os-on-zynq-7020/m-p/568871/highlight/true#M5971

 

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austin
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Registered: ‎02-27-2008

Well, math is math.

 

If you need that delay, then you need it.  Often re-arranging  data lines helps (you do not have to have D0 on D0 of the memory unless there are commands that need to go to the device, you could swap data  bits (as long as you keep track of what you are doing, and not swap anything that cannot be swizzled).

Austin Lesea
Principal Engineer
Xilinx San Jose

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imuguruza
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I forgot to say,

Thanks in advance!
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austin
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Are the traces stripline or microstrip?

 

Depending on the geometry, and if traces are on the surface, or buried, the propagation delay is different.  Your value (6.5 ps) is neither of the above types, so perhaps it is your actual extracted value?

 

Austin Lesea
Principal Engineer
Xilinx San Jose
imuguruza
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Hi @austin thanks for your fast response,

 

Striplines, I'm routing DDR signals in inner layers not in top & bottom, so the 6.5ps/mm delay could not be accurate. But I have used it to make the calcs and to try to have a better picture of the implications delays have at routing stage.

 

Best regards 

 

imuguruza

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austin
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Well, math is math.

 

If you need that delay, then you need it.  Often re-arranging  data lines helps (you do not have to have D0 on D0 of the memory unless there are commands that need to go to the device, you could swap data  bits (as long as you keep track of what you are doing, and not swap anything that cannot be swizzled).

Austin Lesea
Principal Engineer
Xilinx San Jose

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imuguruza
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Hi @austin,

 

Ok, so I guess that those delay numbers are OK + having a good delay value at striplines would allow me to calculate better the delays I have to insert in each signal. I'm aware of the bit swapping, it's a pity is not possible making similar in A & C to make easier the routing of these buses :-)

 

Best regards,

 

imuguruza

 

 

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imuguruza
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For those whoa are interested, I found a useful app note from analog.

 

Regards

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jg_bds
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@imuguruza :

 

I just stumbled across this post.  I see that it's been answered, and all, but I wanted to comment based on what I saw in your spreadsheet. 

 

It looks like you're trying to normal the flight-times of ALL DDR signals to the same value.  That is unnecessary.  Delay matching needs to be done only on and within 'groups' of signals.  DQS[0]_P/N and DQ[7:0] are one group.  DQS[1]_P/N and DQ[15:8] are another group.  All of the signals in the address/control group (nearly every signal that doesn't start with DQ...) are another group.  The average length of one group need not be the same as the average length of another group. 

 

Please be sure to check out https://www.xilinx.com/support/documentation/user_guides/ug933-Zynq-7000-PCB.pdf, particularly the Dynamic Memory section of Chapter 5.  Note the requirement that "CK traces [to a DDR device must] be equal to or longer than the DQS traces per byte lane."

 

It's also important to see if matching is necessary--in the first place.  Very tight (10 pS) matching is generally only necessary if you're trying to run a DDR  at a Zynq's fastest possible memory speed, using minimal-speed chips.  Check out the de-rating tables in Appendix A of the document above.

 

-Joe G.

 

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