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Visitor
Visitor
1,748 Views
Registered: ‎06-11-2017

Package my current project with AXI interface

Hi everyone,

 

I'm new to vivado.

I have finished my RTL design in ncverilog and I want to package my design with AXI interface in order to connect to PYNQ.

However, the "Create and Package IP" seems to only package my design as IP, rather than package my design as IP with AXI interface.

I am wondering whether can I package my IP with AXI interface by any wizard?

 

thanks!

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4 Replies
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Visitor
Visitor
1,737 Views
Registered: ‎09-03-2017

Re: Package my current project with AXI interface

Hello,

 

I think you can package your design by selecting "Create a new AXI4 peripheral", then you can define your AXI4 interfaces.

 

Regards,

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Visitor
Visitor
1,694 Views
Registered: ‎06-11-2017

Re: Package my current project with AXI interface

hi hoanggiamta,

 

"Create a new AXI4 peripheral" -> "Peripheral" -> "Add interface" -> "Create peripheral" seems only to create an wrapper but does not connect to my design?

 

I was wondering whether can I use some command to add AXI interface with memory mapping such as HLS?

 

thanks!

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Xilinx Employee
Xilinx Employee
1,680 Views
Registered: ‎08-02-2013

Re: Package my current project with AXI interface

If you are using HLS to create your design, the tools can automatically add AXI interfaces. 

 

If you have created an RTL design, you can use the packager to create an AXI wrapper. You then need to manually connect your RTL to the wrapper. If you look through the wrapper code that is generated, you will see sections for use logic. 

 

You can usually ignore most of the generated code, and look for the lines of code where you can link your design.

For example, if you create an AXI (lite) slave, you define a number of register that will be created in the wrapper. You can uses these registers (or the signals that write to them) to connect to your code.

 

All the AXI handshaking is taken care of for you in the wrapper. 

 

There is a simple example of adding some custom logic to an AXI wrapper in lab3 here:

https://www.xilinx.com/support/university/vivado/vivado-workshops/Vivado-embedded-design-flow-zynq.html

 

Cathal

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Visitor
Visitor
1,670 Views
Registered: ‎06-11-2017

Re: Package my current project with AXI interface

Hi Cathal,

 

thanks for your reply!

The Lab3 Example does not take the LED output port in AXI interface.

However, HLS will take all output ports in AXI interface.

I was curious that can I take the output port into AXI interface?

My input/output port are 256bit.

I have tried the following code:

 

// Add user logic here
CORE u_CORE(
.CLK(S_AXI_ACLK),
.RST(S_AXI_ARESETN),
.inV(slv_reg0[0]),
.inX({slv_reg8,slv_reg7,slv_reg6,slv_reg5,slv_reg4,slv_reg3,slv_reg2,slv_reg1}),
.inY({slv_reg16,slv_reg15,slv_reg14,slv_reg13,slv_reg12,slv_reg11,slv_reg10,slv_reg9}),
.inP({slv_reg24,slv_reg23,slv_reg22,slv_reg21,slv_reg20,slv_reg19,slv_reg18,slv_reg17}),
.inQ({slv_reg32,slv_reg31,slv_reg30,slv_reg29,slv_reg28,slv_reg27,slv_reg26,slv_reg25}),
.inK({slv_reg40,slv_reg39,slv_reg38,slv_reg37,slv_reg36,slv_reg35,slv_reg34,slv_reg33}),
.inA({slv_reg48,slv_reg47,slv_reg46,slv_reg45,slv_reg44,slv_reg43,slv_reg42,slv_reg41}),
.inB({slv_reg56,slv_reg55,slv_reg54,slv_reg53,slv_reg52,slv_reg51,slv_reg50,slv_reg49}),
.outX1({slv_reg64,slv_reg63,slv_reg62,slv_reg61,slv_reg60,slv_reg59,slv_reg58,slv_reg57}),
.outZ1({slv_reg72,slv_reg71,slv_reg70,slv_reg69,slv_reg68,slv_reg67,slv_reg66,slv_reg65}),
.outV(slv_reg73[0])
);
// User logic ends

 

But I will get the [Synth 8-685] error message.

 

Thanks!

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