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Visitor
Visitor
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Registered: ‎08-06-2020

Petalinux stops working for possible AXI bus issue

Hi all,


I am testing an FPGA design with a PS-ZYNQ and a serious issue occours: Petalinux suddenly stops working, most likely for an AXI bus issue.

What doesn't work, luckely, is how we manage AXI ready signals, even if I don't know why...Do you see something strange in what described here below?

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My FPGA design (Vivado 2019.2) has an AXI memory mapped flow between:

  • The AXI master, given by the M_AXI_GP0 master port of the PS
  • The AXI slave, given by the PL component  AXI_SLAVE_v1_0 (built with "Tools/Create and package new IP"...).

When my internal PL is not ready to accept WR requests from PS, it sends to AXI_SLAVE_v1_0 a signal named wr_PL_busy_i.

At the same way, when my internal PL is not ready to accept RD requests from PS, it sends to AXI_SLAVE_v1_0 a signal named rd_PL_busy_i.

ale11286_0-1605545964026.png

Both of these control signals go into the internal component of the AXI_SLAVE, which is AXI_SLAVE_v1_0_S00_AXI, where they come into play, in the definition of the three AXI signals: AXI awready, AXI wready and AXI arready. The code, autogenerated by Vivado, responsible for the definition of these three AXI ready signals has been modified  as little as possible, like showed here below:

AXI awready generation

ale11286_1-1605545964031.jpeg

AXI wready generation

 

ale11286_2-1605545964036.png

AXI arready generation

 

ale11286_3-1605545964042.png

So, have you any idea  about how to change this part to make Petalinux able to go on working normally, even if AXI slave is not ready to accept master WR/RD requests?

Thanks a lot in advance,

Alessandra

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2 Replies
Moderator
Moderator
238 Views
Registered: ‎03-25-2019

@ale11286,

Why are you adding these signals that do the same job as AXI awready, AXI wready and AXI arready?

 

Best regards,
Abdallah
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Mentor
Mentor
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Registered: ‎06-10-2008

When the master (the PS) performs an AXI read or write, it will stall and wait until the slave finally is ready. So unless your busy signals will not stay active for too long, your approach is wrong.

Instead your slave can report an error on BRESP or RRESP respectively. This will lead to a bus error in linux instead of a stall.

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