cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
11,046 Views
Registered: ‎02-22-2012

Powering off LPDDR2 DRAM

We are looking at making a custom board that would have a Zynq processor with an LPDDR2 DRAM.  I just found out that the LPDDR2 DRAM has very specific power down requirements.  In particular it looks like you have to de-assert the DRAM's CKE pin for a certain amount of time before you are "allowed" to power down.  I'm not sure how that would work, though, since we don't have direct control over the CKE signal.  Given that Zynq supports LPDDR2, how does this work?

0 Kudos
Reply
5 Replies
Professor
Professor
11,044 Views
Registered: ‎08-14-2007

I think you're confusing placing the LPDDR2 in low-power self-refresh mode (power down) with turning off the system (power off).  As far as I'm aware there's no special requirement to power off the LPDDR2 memory.  Normally power-off requirements only specify power supply sequencing to avoid damage to the device.  Obviously the device will lose its contents when powered off completely.

-- Gabor
0 Kudos
Reply
11,023 Views
Registered: ‎02-22-2012

Gabor,

I hope that you are right, but when I read the data sheet it seems to be talking about powering off.  From page 50 of Micron's MT42L128M32D1 datasheet-

 

Power-Off
While powering off, CKE must be held LOW (≤0.2 × VDDCA); all other inputs must be between
VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW.  DQ, DM, DQS, and DQS# voltage levels must be between VSSQ and VDDQ during the power-off sequence to avoid latchup. CK, CK#, CS#, and CA input levels must be between VSSCA and VDDCA during the power-off sequence to avoid latchup.

 

Tx is the point where any power supply drops below the minimum value specified in the Recommended DC Operating Conditions table.


Tz is the point where all power supplies are below 300mV. After Tz, the device is powered
off

.
Required Power Supply Conditions Between Tx and Tz:
• VDD1 must be greater than VDD2 - 200mV
• VDD1 must be greater than VDDCA - 200mV
• VDD1 must be greater than VDDQ - 200mV
• VREF must always be less than all other supply voltages


The voltage difference between VSS, VSSQ, and VSSCA must not exceed 100mV.


For supply and reference voltage operating conditions, see Recommended DC Operating
Conditions table.

 

 

It then talks about "Uncontrolled Power-Off" and says that you must not do it more than 400 times.  Does that mean that uncontrolled power off damages the device, or just that we will lose the data?  By the way, the above text appears to be taken almost word-for-word from the JEDEC LPDDR2 standard.

0 Kudos
Reply
11,022 Views
Registered: ‎02-22-2012

Datasheet attached.

0 Kudos
Reply
Professor
Professor
11,015 Views
Registered: ‎08-14-2007

Unless you intend to remove power from the LPDDR2 while the Xilinx chip is still powered (this is a power supply sequencing issue, but normally the Vcco of the connected banks share a supply with the memory), then it's likely that you won't experience latch-up because the Xilinx I/O's should stay between the related supply and ground.  You might want to add a pull-down to CKE to keep it low from the time the Xilinx part loses its program until power-off.  If you also have resistors to Vtt (not typical with low-power memory) then you might need to account for this by either making sure that the Vtt supply goes down first or using some other termination for the CKE signal.

 

I'm guessing the 400 iteration limit on "uncontrolled" power-off is to prevent device damage.  However note that the Tpoff is quite long at 1 second, so it's likely that any normal power-off sequence could happen many more times.  Also if you found that this data came straight from the JEDEC document, it's also possible that Micron devices are not as succeptible to power-off issues as the data suggests.

 

Still it might make more sense to ask someone at Micron about  this, because it's not really an FPGA issue.  When you remove power from your system, since the FPGA will normally lose at least Vcco (and probably other) supplies at the same time as the LPDDR memory, you can't really use the FPGA to drive CKE low during that time.

-- Gabor
0 Kudos
Reply
Observer
Observer
996 Views
Registered: ‎06-10-2010

Hello,

this thread is rather old, but because the same requirements apply to LPDDR4, and I had the same question for a Zynq UltraScale+ MPSoC, I think the information I got in Xilinx' SR#10464806 is helpful for others, too. It may or may not apply to a 7 Series Zynq.

"When the LPDDR4 isn’t active CKE will be driven low, and if you’re entering a controlled power down state then setting the system reset (PS_SRST_B) or the power on reset (PS_POR_B) LOW will keep the PS in reset and will keep CKE low. Both of these signals can be controlled by the Zynq PMU firmware and there are various methods on how to do this through PMU firmware or Platform Management hooks. From there the I/O voltage level is determined by the VCC0 rail for the PS DDR banks which are controlled by your PMU. The recommended ramping down sequence from DS925 is VCC0_PSIO first followed by the rest of the rails, so CKE will remain low if the guidelines are followed. In the case of an unexpected power loss it will be up to your system design to leverage the PMU or external logic to manage the CKE signal or generate a reset to the Zynq to make sure the LPDDR4 power down is controlled."

I conclude from this: If your power down sequencing asserts a Zynq Reset before turning off supplies, and then turns supplies off in the correct order, all LPDDR requirements for controlled power down are met. In this case there is no need for software intervention setting any memory controller registers prior to power down.

Best regards, David

0 Kudos
Reply