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vickyisro
Visitor
Visitor
1,064 Views
Registered: ‎01-09-2020

Problem with AXI DMA data transfer

Hi,

I have been trying to use axi dma for data transfer from PL to PS but no success.

I have a program which generated serial data samples in PL, another IP converts it to parallel and saves in block ram. Another IP reads data from block ram and dumps it into ax AXI data stream FIFO.  This much part i have simulated and checked it works fine.

Now i have added ZYNQMPSOC  PS and AXI DMA to take data from AXI data stream FIFO to PS.

But it doesn't work. I have used the sample program provided for DMA transfer in Vitis Examples and modified it to use only recieve part not sending as  i am not sending the data from PS to PL.

Also once i add ps part .. i am not able to debug it using ILAs hardware manager in Vivado. It doesn't load the .ilx file in hardware manager.

 

I have attached the design and C program please help. I am using vivado 2019.2 and vitis.

 

 

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8 Replies
dgisselq
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Registered: ‎05-21-2015

@vickyisro,

Why are you feeding the design with a constant reset signal?  Many Xilinx components require a reset.  Not only that, they require a reset that lasts several clocks in duration.  Xilinx's AXI guide indicates that the reset should last at least 16 clocks.  Although 16 clocks seems overkill to me, I have seen multiple Xilinx components requiring multiple clocks of reset before they'd get into a working state.

Dan

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vickyisro
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Registered: ‎01-09-2020

Hi,

 

Thanx for replying.

I have changed the reset to multiple clocks and it seems to be working now.

But i get error aafter transferrring the data .

DMA Status register value = 0x0011 and

DMA IrqStatus value = 0x5000

I am not able to figure out why this error is coming and how to correct it.

PLease let me know if you have any solution for this.

 

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dgisselq
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Registered: ‎05-21-2015

@vickyisro ,

The most common DMA error is to read or write data from a custom IP generated from Xilinx's demo design.  This design will lock up your bus, while also achieving much less than the full bus bandwidth.

The second most common DMA error is to read or write data from a non-existent address.

Check your addressing to make certain that the addresses are valid.  Beware of any virtual to physical translations.

The third most common DMA problem is to write to memory and then to read stale data from the cache.  It doesn't sound like you've gotten this far yet.

Dan

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joancab
Teacher
Teacher
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Registered: ‎05-11-2015

 

I struggled with a similar situation. Eventually I concluded (not proven) that DMA hangs if it receives data (stream) before being set up for the transfer, so I wrote my function in HLS and forgot about it. You can probably easily write a DMA block in HLS so you know its behavior.

adem369
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Registered: ‎02-18-2019

Are you sending tlast signal to DMA correctly?

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joancab
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Registered: ‎05-11-2015

@adem369 

Even with that funny things happen. I wonder what is the purpose of Tlast if DMA transfers are started with a specified length.

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dgisselq
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Registered: ‎05-21-2015

@joancab ,

The purpose of TLAST in Xilinx's stream to memory DMA application is to terminate the memory copy early.  This way you can send network packets, where you might know the maximum packet length but not the actual packet length.  You might configure the DMA with the maximum length, but then it would stop early when the actual packet end is detected.

This doesn't excuse the fact that the core will lock up if data arrives early, before it has been configured for a transfer.

Dan

adem369
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Registered: ‎02-18-2019

You must send tlast signal before or at the specified length. If you send tlast signal after the specified length or if you dont send tlast signal, DMA will give you an error. DMA stops when it receives tlast signal, even though the specified number of bytes are not transferred.

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