11-17-2020 02:53 AM
I've been trying to use the mms interface of the AXI datamover , to move data from the ddr to stream. As you can see in the screenshot, the first and second packets have a latency of 2 cycles, however the third packet has a latency of 16 cycles from the end of the second packet. This pattern repeats itself, and i was wondering if someone knew why is this happening ?
Bellow, you will find attached screenshots of the configuration of the datamover, a screenshot of the packets, as seen from ILA and a screenshot of the given commands
AXI datamover configuration :
As you can see i have the xcache enabled. The value if xcache is 1.
11-17-2020 04:14 AM
Wow, that is *really* pitiful.
I'm tempted to believe the problem is on the MM side, since TREADY holds high through the whole transfer. Let me ask, therefore, how is your AXI interconnect configured between the Zynq and this MM2S?
11-17-2020 04:31 AM
Hello @dgisselq ,
thanks for the reply.
I'm sending you a screenshot of my block diagram and the configuration of the axi interconnect
the said axi datamover is the axi datamover 0 and as you can see, it is connected with an axi interconnect to HP0 of the zynq.
The configuration of the axi interconnect is :
As for the TREADY it is designed to always be 1, since all the data go to a MISR for consuming
11-17-2020 08:13 AM
The custom optimization strategy is the default selection of vivado, i haven't created a custom strategy.
However, when i changed to maximize performance :
the performance improved a bit but still there were some packets with big latencies :
11-17-2020 08:41 AM
Yes, that is better, but it is still pitiful.
If the interconnect is optimized for performance and that's what you are getting, then let me ask ... what does the AXI bus look like on the other side of the interconnect? Between the PS and the PL? Can you tap it there? That might tell us more about the performance you are getting, since that's where I expect any residual problems might be lying.
11-18-2020 07:34 AM
As you suspected there seems to be a problem on the mm side. For some reason the DDR has a lot of delay when sending some of the packets. Which i don't know where they come from. Any ideas of narrowing the problem down would be very useful.
11-18-2020 08:14 AM