10-24-2018 04:39 AM
I am currently learning to use QEMU for validation of a simple read & write application in zc702. I have completed the following steps:
a) created .bd file in Vivado with Zynq PS having only bram_memory_generator to perform read/write operation.
b)generated bitstream and imported .hdf to Xilinx SDK tool
c) created an application (c-code) to WR data and obtained .elf file
d) launched QEMU emulator using command line. I have downloaded only the .elf file using QEMU command. No data has been written/read back from PL side. The output is shown in the attached screenshot.
I am not sure whether the .elf file is a composite bitstream (i.e s/w application + bitstream).
1) Does QEMU support configuration of Programmable Logic (PL) portion of Zynq7000/ZynqMP or only the PS portion of the SoC?
2) If yes, how to download the <test>.bit (bitsream) in QEMU?
Kindly share information to resolve this issue, shown in screenshot.
Thanks & Regards.
06-20-2019 01:30 AM
06-20-2019 01:42 AM
You cannot program the PL in QEMU. The QEMU will use the devicetree and emulated models to emulated your system.
06-21-2019 12:53 AM
hello @stephenm , thanks for your answer , as i understand from what you say , steps :
-Doing the design through vivado
-Doing application using sdk , and generating the HDF ( which contain the device tree)
-then using HLS to generate SystemC
-Using the Libsystemctlm into my project
is that right ??
and when you say the qemu use the device tree ? the device tree by default come with my description hardware generated in sdk or should i build manually that device tree ? other question the libsystemcsoc is usefull for any project or its just for the demo showin by xilinx , thanks a lot @stephenm
06-21-2019 02:14 AM
What are you trying to achieve with the QEMU? For example, if you are designing a custom RTL IP, and want to test this, then you woould use the co-simulation to see how tis would preform in your system. You could also just use the verification IP in Vivado to test traffic to and from your IP.
However, if you want to test your application on a SoC, then you wouldnt really need to co-sim.
So, it really depends on what you are trying to test, and to set up a test environment that best meets your needs.
With respect to the devicetree, there is a DT for the Machine (use the default), and then one for your embedded system. For this one, you can create this using the DTG (devicetree generator) using your HDF as an input.
06-21-2019 02:35 AM
Thanks for your information , i am working on cosimulation , as it is mentionnated in user guide of QEMU , QEMU just emulate the PS part , so if i do a design with PS and PL , and an application , i should use cosimulation to let the PS cnnect to PL to enable ports for example , i found thati have to use SystemC-tlm which is given by Xilinx in the libsystemctlmSoc , but i just want to know if that library support any project or its just for the example demo of xilinx, then can you told if steps below are right or i have to do other thing :
for example lets say am doing a read/write between PS and PL (BRAM) through Axi interconnect: steps:
1- Vivado degin 2-application sdk 3- generating systemC for the design using Hls -integrate the libsystemtlm to my project - using qemu with .elf application ?
and should i put my hdf design or lets say the systemc generated for the design there is a way to put it as argument to qemu or integrate it into the libsystemtlmsoc ???
sorry i make a lot of question but i really need a help and have no much time , thanks a lot
06-21-2019 02:42 AM
My project is about cosimulation , emulating the SW and HW together , first i have to validate this by a simple design using ZynqMpsoC Ps and a simple design , and after i will use this in order to do cosim for Zynq ultrascale + RFSOC in order to get data signals without having a board , i have no board and my project oblige me with this method
07-19-2019 02:59 PM