Reading from DDR using AXI master ip through HP on Zynq
I am trying to read ddr data in burst mode using axi master ip through HP port on ZYNQ. At the beginning, I write data from SDK to the DDR memory, then I send start signal to the AXI master IP. IP then reads data from DDR.
My problem is that while reading, in 1st transaction pulse, garbage value(default ddr data) is displaying in ILA. After some delay correct value(which i wrote from SDK to DDR) will display in ILA.
any idea how to ignore garbage value??
how we can disable caches??
how we can flush l2 cache??
i tried with void Xil_L2CacheFlushRange(unsigned int adr, unsigned len) funtionbut syntax error is coming. Any example code to flush L2 cache??