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asai9493
Adventurer
Adventurer
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Registered: ‎12-10-2020

Register in technical manual of ZYNQ

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Hello everyone!

I am reading the technical reference manual of ZYNQ.

In the technical manual there is a list with details of the registers in Zynq.

How can I use these details? Address? Width? Is it helpful in programming?

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derekm_
Voyager
Voyager
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Registered: ‎01-16-2019

The drivers that you have been using in SDK are based on these registers. For example, for the  PS GPIO driver, if you look in xgpiops_hw.h you will be able to find some of the registers that appear in Appendix B.19 of the TRM. The files with the "_hw" designation are very low level, close to the hardware. In SDK for the GPIO driver you generally use xgpiops.h, which itself makes use of the functions in xgpiops_hw.h.

When (digital/hardware) engineers design each block in silicon, the registers are used to control the block. In software you could use low-level read/write functions to access the registers and control the block, but instead drivers are developed (by software engineers) to make the job a lot easier (for other software engineers). The drivers contain all the functionality you need so that you don't have to understand the device at a low level. It's also better for re-usability/portability purposes.

You could design your own drivers if you wanted, either using xgpiops_hw.h as a base (using the PS GPIO as an example), or you could even start with a totally blank slate and create completely new drivers using Xil_In32(), Xil_Out32(), etc, as your base. It would be a good exercise when you are starting out in embedded programming.

Example details in xgpiops_hw.h:

 

 

#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */

 

 

 

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derekm_
Voyager
Voyager
361 Views
Registered: ‎01-16-2019

The drivers that you have been using in SDK are based on these registers. For example, for the  PS GPIO driver, if you look in xgpiops_hw.h you will be able to find some of the registers that appear in Appendix B.19 of the TRM. The files with the "_hw" designation are very low level, close to the hardware. In SDK for the GPIO driver you generally use xgpiops.h, which itself makes use of the functions in xgpiops_hw.h.

When (digital/hardware) engineers design each block in silicon, the registers are used to control the block. In software you could use low-level read/write functions to access the registers and control the block, but instead drivers are developed (by software engineers) to make the job a lot easier (for other software engineers). The drivers contain all the functionality you need so that you don't have to understand the device at a low level. It's also better for re-usability/portability purposes.

You could design your own drivers if you wanted, either using xgpiops_hw.h as a base (using the PS GPIO as an example), or you could even start with a totally blank slate and create completely new drivers using Xil_In32(), Xil_Out32(), etc, as your base. It would be a good exercise when you are starting out in embedded programming.

Example details in xgpiops_hw.h:

 

 

#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */

 

 

 

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